Induction Devices LLC v. JPMorgan Chase Bank NA

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Induction Devices LLC (Texas)
  • Defendant: JPMorgan Chase Bank, N.A. (United States)
  • Plaintiff's Counsel: Shea | Beaty PLLC
• Case Identification: 2:26-cv-00194, E.D. Tex., 03/10/2026
• Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because the Defendant maintains a place of business in the district and conducts business there.
• Core Dispute: Plaintiff alleges that Defendant's contactless credit cards infringe seven U.S. patents related to various semiconductor circuit designs and methods, including power management, signal processing, and data communication.
• Technical Context: The patents-in-suit relate to fundamental circuit-level technologies used in microcontrollers and integrated circuits for functions such as system resets, signal multiplexing, power-on-reset, and secure data handling.
• Key Procedural History: The complaint notes that U.S. Patent No. 7,899,145 was previously litigated in the Western District of Texas but the cases were resolved before any substantive matters were addressed. The complaint also notes that U.S. Patent Nos. 6,868,500 and 6,931,465 have expired, and Plaintiff seeks damages only for the period of infringement prior to their expiration dates.

Case Timeline

Date	Event
2000-10-26	Priority Date for U.S. Patent No. 6,868,500
2001-03-31	Priority Date for U.S. Patent No. 6,931,465
2005-03-15	Issue Date for U.S. Patent No. 6,868,500
2005-08-16	Issue Date for U.S. Patent No. 6,931,465
2005-09-02	Priority Date for U.S. Patent No. 7,899,145
2006-01-26	Priority Date for U.S. Patent No. 7,449,926
2006-12-21	Priority Date for U.S. Patent No. 8,190,885
2007-03-09	Priority Date for U.S. Patent No. 8,370,543
2007-04-17	Priority Date for U.S. Patent No. 8,543,628
2008-11-11	Issue Date for U.S. Patent No. 7,449,926
2011-03-01	Issue Date for U.S. Patent No. 7,899,145
2012-05-29	Issue Date for U.S. Patent No. 8,190,885
2013-02-05	Issue Date for U.S. Patent No. 8,370,543
2013-09-24	Issue Date for U.S. Patent No. 8,543,628
2020-03-10	Alleged Damages Period Begins for Expired Patents
2021-01-01	Prior litigation involving the '145 patent initiated
2022-06-09	Expiration Date for U.S. Patent No. 6,931,465
2023-01-23	Expiration Date for U.S. Patent No. 6,868,500
2026-03-10	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,449,926 - Circuit for Asynchronously Resetting Synchronous Circuit

• Issued: November 11, 2008

The Invention Explained

• Problem Addressed: The patent describes a challenge in designing reset circuits for synchronous systems, such as those with a CPU and RAM. Resetting a system with a signal that is asynchronous to the system's clock can lead to data loss or instability (e.g., in a RAM) (Compl. ¶10; Compl. ¶11, Compl. ¶¶col. 1:36-41). However, if the system is operating abnormally, an immediate asynchronous reset may be necessary to restore proper function.
• The Patented Solution: The invention is a reset signal generation circuit that dynamically chooses the type of reset signal to generate. It includes an "operation detection circuit" to determine if a synchronous circuit (like a CPU) is operating "normally or abnormally" '926 Patent, abstract Based on this determination, a "signal control circuit" generates either a reset signal that is synchronous with the internal clock (for normal operation, preserving data) or one that is asynchronous (for abnormal operation, forcing an immediate initialization) Compl. ¶11 '926 Patent, col. 2:1-7 '926 Patent, col. 6:58-7:6
• Technical Importance: This approach aims to enhance circuit reliability by providing the stability of a synchronous reset during normal operations while retaining the fail-safe capability of an immediate asynchronous reset during system malfunctions Compl. ¶11

Key Claims at a Glance

The complaint asserts at least independent claim 1 Compl. ¶44

• Claim 1: A reset signal generation circuit for a synchronous circuit, comprising:
  • an operation detection circuit for detecting whether the synchronous circuit is operating normally or abnormally and for generating an operation detection signal; and
  • a signal control circuit, connected to the operation detection circuit, for generating the first reset signal based on a system reset signal, the clock signal, and the operation detection signal,
  • wherein the signal control circuit generates the first reset signal that is synchronous to the clock signal in response to the system reset signal when the synchronous circuit is operating normally, and
  • wherein the signal control circuit generates the first reset signal that is asynchronous to the clock signal in response to the system reset signal when the synchronous circuit is operating abnormally.

U.S. Patent No. 7,899,145 - Circuit, System, and Method for Multiplexing Signals with Reduced Jitter

• Issued: March 1, 2011

The Invention Explained

• Problem Addressed: In complex electronic systems, multiplexers are used to select one of several clock or data signals for a given path. The patent states that conventional multiplexer designs can introduce "crosstalk and power supply noise" when signals are routed in close proximity, which degrades performance by increasing signal timing variations known as "jitter" Compl. ¶16 '145 Patent, col. 2:54-63
• The Patented Solution: The patent discloses a multiplexer circuit designed to reduce jitter. The core idea is to physically and electrically isolate the signal paths. This is achieved by distributing the logic gates of the multiplexer into "separate power supply domains" and using a logic block to supply a "static control signal" that deactivates all but one of the input signals at any given time Compl. ¶17 '145 Patent, col. 3:13-28 By ensuring only one active signal is present at the inputs to the logic gates, the potential for crosstalk and noise injection is significantly reduced Compl. ¶17 '145 Patent, col. 3:26-34
• Technical Importance: By minimizing jitter in clock networks, this design can improve the timing, performance, and reliability of high-speed synchronous systems Compl. ¶16 '145 Patent, col. 1:47-52

Key Claims at a Glance

The complaint asserts at least independent claim 10 Compl. ¶54

• Claim 10: A system, comprising:
  • a circuit comprising two logic gates and a first logic block and a second logic block, each arranged within a separate power supply domain, wherein:
  • a first of the two logic gates is operatively coupled with a first signal;
  • a second of the two logic gates is operatively coupled with a second signal; and
  • a second logic block operatively coupled with one of the first and second signals, depending on a state of a control signal; and
  • a system component coupled to the second logic block.

Multi-Patent Capsules

• Patent Identification: U.S. Patent No. 8,190,885, Non-Volatile Memory Sub-System Integrated with Security for Storing Near Field Transactions, issued May 29, 2012.

• Technology Synopsis: The patent is directed to a memory module that integrates a security processor, non-volatile memory, and a Near Field Communication (NFC) component. This integration creates a secure environment for processing and storing NFC transaction data, with the security processor enforcing access rights to memory partitions Compl. ¶¶21-22

• Asserted Claims: At least claims 1 and 3 Compl. ¶64

• Accused Features: The complaint alleges that Defendant's "contactless credit cards" infringe the '885 patent Compl. ¶64

• Patent Identification: U.S. Patent No. 8,370,543, Busy Detection Logic for Asynchronous Communication Port, issued February 5, 2013.

• Technology Synopsis: The patent describes systems and methods for synchronizing access to resources between components operating in different time domains (e.g., a processor and a memory device with different clocks). The invention aims to achieve this synchronization without requiring high-speed clocks or imposing minimum pulse width requirements on control signals Compl. ¶¶25-27

• Asserted Claims: At least claim 16 Compl. ¶74

• Accused Features: The complaint alleges that Defendant's "contactless credit cards" infringe the '543 patent Compl. ¶74

• Patent Identification: U.S. Patent No. 8,543,628, Method and System of Digital Signal Processing, issued September 24, 2013.

• Technology Synopsis: The patent is directed to a dynamically reconfigurable digital filtering system on a chip. A microcontroller uses instruction sets to configure a controller and an address-calculation device, which in turn select filter-coefficients for a data path device to use in performing digital signal processing on incoming data Compl. ¶¶30-31

• Asserted Claims: At least claim 1 Compl. ¶84

• Accused Features: The complaint alleges that Defendant's "contactless credit cards" infringe the '628 patent Compl. ¶84

• Patent Identification: U.S. Patent No. 6,868,500, Power on Reset Circuit for a Microcontroller, issued March 15, 2005.

• Technology Synopsis: The patent describes a Power on Reset (POR) circuit that provides multi-level POR capabilities and post-boot-up power stability functions. The invention aims to address issues in prior art POR circuits by using existing system resources to manage power states both during and after boot-up, without requiring additional dedicated resources Compl. ¶¶34-37

• Asserted Claims: At least claim 22 Compl. ¶94

• Accused Features: The complaint alleges that Defendant's "contactless credit cards" infringe the '500 patent Compl. ¶94

• Patent Identification: U.S. Patent No. 6,931,465, Intelligent, Extensible SIE Peripheral Device, issued August 16, 2005.

• Technology Synopsis: The patent discloses a peripheral device with an intelligent serial interface engine (SIE) that can autonomously process basic protocol requests from a host. Requests that the SIE cannot handle are passed to an external processor, thereby reducing the external processor's overhead and improving performance compared to conventional SIEs that act merely as conduits Compl. ¶¶40-42

• Asserted Claims: At least claim 13 Compl. ¶99

• Accused Features: The complaint alleges that Defendant's "contactless credit cards" infringe the '465 patent Compl. ¶99

III. The Accused Instrumentality

Product Identification

• The complaint identifies the accused instrumentalities as "contactless credit cards" provided and used by Defendant Compl. ¶44 Compl. ¶54

Functionality and Market Context

• The complaint does not provide specific technical details regarding the internal architecture or operation of the accused contactless credit cards. The allegations are framed at a high level, stating that the cards are made, used, sold, or imported by the Defendant and that their use constitutes infringement Compl. ¶44 The complaint alleges these products are marketed and used by Defendant's partners, clients, and customers across the country Compl. ¶46 No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint does not contain narrative infringement theories or claim charts within the body of the document. Instead, it alleges infringement and states that an "Exemplary infringement analysis" is provided in external exhibits (e.g., Exhibit A-1 for the '926 patent, Exhibit B-1 for the '145 patent), which are not attached to the publicly filed complaint Compl. ¶45 Compl. ¶55 The complaint asserts that this analysis is preliminary and reserves the right to amend it Compl. ¶45 Compl. ¶55

• Identified Points of Contention:
  • Applicability of Technology: A potential point of contention for the '926 patent is whether the circuitry within a contactless credit card, a highly specialized and power-constrained device, implements a sophisticated CPU monitoring and dual-mode (synchronous/asynchronous) reset system as claimed. The dispute may center on what constitutes an "operation detection circuit" that distinguishes "normal" from "abnormal" CPU operation in the context of such a device.
  • Scope and Implementation: For the '145 patent, a key question may be whether the multiplexing circuitry within the accused cards is arranged in "separate power supply domains" as required by claim 10. The analysis will likely focus on the physical and electrical layout of the semiconductor die within the cards and whether it meets the structural requirements of the claim, raising a question of claim scope.

V. Key Claim Terms for Construction

For the '926 Patent (Claim 1)

• The Term: "operation detection circuit for detecting whether the synchronous circuit is operating normally or abnormally"
• Context and Importance: This term is the core of the invention's dynamic functionality. Its construction will determine what type of monitoring or feedback mechanism is required to practice the claim. The infringement analysis depends on whether the accused cards contain a circuit that performs this specific detection function, as opposed to a more generic reset or watchdog timer.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim language itself is functional, suggesting any circuit that performs the function of detecting normal/abnormal operation could suffice.
  • Evidence for a Narrower Interpretation: The specification describes a specific embodiment where the operation detection circuit is an up-counter that is periodically cleared by the CPU; if the CPU operates abnormally and fails to send the clear signal, the counter value exceeds a threshold, indicating an abnormal state '926 Patent, col. 4:13-46 A defendant may argue the claim should be limited to this or a similar implementation.

For the '145 Patent (Claim 10)

• The Term: "each arranged within a separate power supply domain"
• Context and Importance: This structural limitation is central to the patent's proposed solution for reducing jitter by isolating components. The infringement case will hinge on whether the accused products' physical chip layout constitutes "separate power supply domains." Practitioners may focus on this term because it requires a specific physical and electrical configuration that may not be present in all multiplexer designs.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The term could be construed to mean any form of electrical isolation between the power supplies of the different logic gates, even without significant physical separation on the die.
  • Evidence for a Narrower Interpretation: The specification describes arranging logic gates within different power supply "'islands,' each coupled to a different power bus" and notes that "a relatively high substrate resistance also functions to provide isolation between the power supply islands" '145 Patent, col. 3:30-37 This language suggests a more stringent requirement for physical separation and distinct power connections, which could support a narrower construction of the term.

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement under 35 U.S.C. § 271(b). The factual basis alleged is that Defendant aids and abets infringement by "advertising and distributing the Accused Instrumentalities and providing instruction materials, training, and services regarding the Accused Instrumentalities" with specific intent or willful blindness Compl. ¶49 Compl. ¶59
• Willful Infringement: The complaint alleges willful infringement based on Defendant's knowledge of the patents and the alleged infringement, stating Defendant was made aware "at least as early as the filing of this Complaint" Compl. ¶47 Compl. ¶57 The claim for willfulness appears to be based on alleged post-suit knowledge.

VII. Analyst's Conclusion: Key Questions for the Case

1. Technical Applicability: A fundamental issue will be whether the specific circuit-level architectures described in the patents-in-suit, which address general problems in microcontrollers and synchronous systems, are actually implemented within the highly specialized, cost-sensitive, and power-constrained integrated circuits of modern contactless credit cards. The case may turn on whether these foundational technologies read on the specific, proprietary designs used in the accused products.
2. Evidentiary Sufficiency: Since the complaint's technical infringement allegations are contained entirely within external exhibits that were not provided, a primary question for the early stages of litigation will be the sufficiency of the factual basis for Plaintiff's claims. The proceedings will likely focus on what pre-suit investigation Plaintiff conducted to support its belief that the non-public, internal workings of Defendant's credit cards practice each element of the asserted claims.
3. Claim Scope: The dispute may center on the construction of key structural terms, such as "separate power supply domain" ('145 patent) and functional terms like "operation detection circuit" ('926 patent). The ultimate determination of infringement could depend on whether these terms are interpreted broadly to cover any functionally similar structure or narrowly to the specific embodiments disclosed in the patents.