Chip Packaging Tech LLC v. Renesas Electronic Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Chip Packaging Technologies, LLC (Texas)
  • Defendant: Renesas Electronics Corporation (Japan)
  • Plaintiff’s Counsel: Blue Peak Law Group LLP
• Case Identification: 2:26-cv-00120, E.D. Tex., 02/17/2026
• Venue Allegations: Plaintiff alleges that because Defendant is not a resident of the United States, venue is proper in any judicial district under 28 U.S.C. § 1391(c)(3).
• Core Dispute: Plaintiff alleges that Defendant’s semiconductor products, including its Gallium Nitride (GaN) Field-Effect Transistors (FETs), Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), and Load Switches, infringe four patents related to semiconductor packaging technologies.
• Technical Context: The dispute centers on the physical structures and manufacturing methods for packaging semiconductor die, a critical process for protecting integrated circuits and providing electrical connections for use in electronic devices.
• Key Procedural History: The complaint does not reference any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the asserted patents.

Case Timeline

Date	Event
2007-07-23	U.S. Patent No. 8,258,611 Priority Date
2012-07-17	U.S. Patent No. 8,643,189 Priority Date
2012-09-04	U.S. Patent No. 8,258,611 Issues
2014-02-04	U.S. Patent No. 8,643,189 Issues
2014-07-02	U.S. Patent No. 9,263,299 Priority Date
2016-02-16	U.S. Patent No. 9,263,299 Issues
2017-12-20	U.S. Patent No. 10,192,837 Priority Date
2019-01-29	U.S. Patent No. 10,192,837 Issues
2026-02-17	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,258,611 - "Leadframe Structure For Electronic Packages," issued September 4, 2012

The Invention Explained

• Problem Addressed: The patent’s background describes the risk of wire bond breakage in semiconductor packages, particularly for "downbonds" that connect the die to an electrical ground on the die-pad (’611 Patent, col. 1:28-35). This failure is often caused by thermo-mechanical stress, which leads to the plastic moulding compound delaminating (peeling away) from the underlying metal leadframe, physically tearing the delicate bondwire from its connection point ('611 Patent, col. 1:40-51).
• The Patented Solution: The invention introduces a specially designed "barrier area" that connects the die-pad to the wire bonding area ('611 Patent, abstract). This barrier, typically a long and narrow metallic structure, is configured to act as a dam, arresting the propagation of delamination that begins elsewhere on the die-pad and preventing it from reaching the critical bonding location, thus preserving the wire bond's integrity ('611 Patent, col. 2:54-65; '611 Patent, fig. 3B).
• Technical Importance: This structural feature aims to improve the long-term reliability of packaged semiconductor devices by mitigating a common failure mode without altering the fundamental electrical design ('611 Patent, col. 1:52-56).

Key Claims at a Glance

• The complaint asserts independent Claim 1 (Compl. ¶33).
• Essential elements of Claim 1 include:
  • A leadframe structure for an electronic package comprising:
  • a die-pad configured and arranged for die attachment,
  • a bonding area, and
  • a barrier area having a barrier structure connecting the die-pad and the bonding area and configured and arranged with a length and width, at a connection between the barrier and the die-pad, that mitigates the delamination of a moulding compound from the barrier as the moulding compound delaminates from a portion of the die-pad adjacent the connection between the barrier and the die pad.

U.S. Patent No. 9,263,299 - "Exposed Die Clip Bond Power Package," issued February 16, 2016

The Invention Explained

• Problem Addressed: The patent addresses the need to create semiconductor power packages with enhanced thermal performance (better heat dissipation) and minimal internal electrical resistance, which are critical for high-power devices in compact form factors (’299 Patent, col. 1:47-55).
• The Patented Solution: The patent discloses a method of manufacturing where active device die are mounted on a "temporary carrier," such as an adhesive tape ('299 Patent, col. 4:9-12). Solder paste is applied to the die's bond pads, and a pre-formed lead frame is attached, with its upper portions contacting the solder and its lower portions contacting the carrier ('299 Patent, abstract). After solder reflow and encapsulation, the final package features an exposed die underside for direct thermal contact and a low-resistance "clip bond" connection between the die and the leads ('299 Patent, col. 1:50-55).
• Technical Importance: This manufacturing process facilitates the production of power packages with superior thermal management and electrical efficiency, enabling higher performance in smaller physical footprints ('299 Patent, col. 1:47-55).

Key Claims at a Glance

• The complaint asserts independent Claim 1, a method claim (Compl. ¶49).
• Essential elements of Claim 1 include:
  • A method for packaging an integrated circuit (IC) device, comprising:
  • mounting a plurality of active device die onto a temporary carrier, each die having bond pads and a solderable conductive underside surface after back-grinding;
  • dispensing a solder paste onto the bond pads;
  • attaching a lead frame to the temporary carrier, where upper lead frame portions contact the solder paste and lower lead frame portions contact the temporary carrier; and
  • reflowing the solder to connect the upper lead frame portions and the bond pads.

U.S. Patent No. 10,192,837 - "Multi-Via Redistribution Layer For Integrated Circuits Having Solder Balls," issued January 29, 2019

• Technology Synopsis: The patent addresses the problem of thermal-induced cracking and high electrical resistance in wafer-level chip-scale packages (WLCSPs) (’837 Patent, col. 1:49-53). The proposed solution is a redistribution layer (RDL) design that places multiple via structures directly underneath the footprint of a solder ball, creating a more robust and lower-resistance electrical connection to the underlying metal layer of the integrated circuit ('837 Patent, abstract).
• Asserted Claims: Independent Claim 11 is asserted (Compl. ¶70).
• Accused Features: The complaint accuses the multi-via RDL structures found in the Renesas GreenFET Load Switch product line, including the SLGM1746C and SLG59M1746C products (Compl. ¶69).

U.S. Patent No. 8,643,189 - "Packaged Semiconductor Die With Power Rail Pads," issued February 4, 2014

• Technology Synopsis: The patent addresses the challenge of providing numerous power and ground connections to a semiconductor die without increasing package size or introducing electrical noise (’189 Patent, col. 1:40-45). The invention describes using at least one large "power rail pad" on the die surface, which serves as a common connection point for multiple internal circuit nodes, thereby simplifying the wire bonding layout and reducing the number of external connections required ('189 Patent, abstract).
• Asserted Claims: Independent Claim 15 is asserted (Compl. ¶88).
• Accused Features: The complaint accuses the power rail pad structures in the Renesas SuperGaN GaN FET product line, specifically identifying the TP65H150BG4JSG product (Compl. ¶87).

III. The Accused Instrumentality

Product Identification

The complaint targets multiple product families, including the Renesas SuperGaN GaN FET product line, the Renesas REXFET Power MOSFET product line, and the Renesas GreenFET Load Switch product line (Compl. ¶26). Specific exemplary products are identified for each asserted patent (Compl. ¶¶32, 48, 69, 87).

Functionality and Market Context

The accused products are power semiconductor components, such as transistors and switches, used in a variety of electronics for power management and control (Compl. ¶3). The complaint alleges these products are made available for purchase in the United States directly from Renesas's website and through authorized distributors (Compl. ¶¶26-29). The complaint includes a screenshot from the Digi-Key distributor website showing one of the accused product families available for purchase (Compl. p. 6).

IV. Analysis of Infringement Allegations

U.S. Patent No. 8,258,611 Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a die-pad configured and arranged for die attachment,	The accused product, TP65H070G4LSGB-TR, includes a die-pad for die attachment, as allegedly shown in annotated X-ray images.	¶36	col. 5:45-46
a bonding area	The accused product includes a bonding area, as allegedly shown in annotated X-ray images.	¶37	col. 5:48-50
a barrier area having a barrier structure connecting the die-pad and the bonding area and configured and arranged with a length and width, at a connection between the barrier and the die-pad, that mitigates the delamination...	The accused product allegedly includes a barrier structure connecting the die-pad and bonding area that is configured to mitigate delamination, as shown in annotated X-ray images (Compl. p. 13).	¶38	col. 6:30-36

• Identified Points of Contention:
  • Functional Scope: A central question may be whether the accused structure performs the claimed function of "mitigat[ing] the delamination" of the moulding compound. The analysis will depend on the construction of this functional language and the evidence presented to show that the accused structure achieves this result, rather than being a conventional leadframe feature with a different purpose.
  • Evidentiary Basis: The complaint’s allegations are based on "information and belief" and an analysis of package photos and X-ray images (Compl. ¶36). The actual performance and intent behind the design of the accused structure will likely require technical discovery to substantiate.

U.S. Patent No. 9,263,299 Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
mounting a plurality of active device die, into predetermined positions, onto a temporary carrier, each said active device die having bond pads, each of said active device die having a solderable conductive surface on its underside...	The accused products are allegedly manufactured by a process that mounts multiple active die, which have bond pads and a solderable underside, onto a temporary carrier.	¶¶52-53	col. 3:9-14
dispensing a solder paste onto the bond pads on the plurality active device die;	The manufacturing process allegedly dispenses solder paste onto the bond pads of the active die.	¶54	col. 3:32-33
attaching a lead frame to the temporary carrier, the lead frame having an array of device positions which correspond to the predetermined positions of the plurality of active device die, wherein upper lead frame portions contact the solder paste... and lower lead frame portions contact the temporary carrier	The manufacturing process allegedly uses an "undiced lead frame" with an array of positions corresponding to the die array (Compl. p. 20), where upper parts of the lead frame contact the solder and lower parts contact the temporary carrier. The complaint alleges this occurs before the array is diced into individual units.	¶¶55-57	col. 3:35-42
reflowing the solder so that a connection is made between the upper lead frame portions and the bond pads...	The process allegedly reflows the solder to form an electrical and mechanical connection, with EDS mapping allegedly showing a silicon die with lead-based solder on its top and bottom surfaces.	¶58	col. 3:45-49

• Identified Points of Contention:
  • Process vs. Product: The asserted claim is for a method of manufacturing. The complaint alleges infringement by products "made using the patented methods" (Compl. ¶48). A key issue will be whether Plaintiff can prove, through discovery and analysis, that Defendant’s proprietary manufacturing process includes each of the claimed steps, as the complaint acknowledges these steps are not public (Compl. ¶55).
  • Technical Equivalence: The infringement analysis may turn on whether the materials and structures used in Defendant's process (e.g., its specific type of carrier, lead frame design) correspond to the elements recited in the claim, either literally or under the doctrine of equivalents.

V. Key Claim Terms for Construction

Term from the ’611 Patent: "mitigates the delamination"

• The Term: "mitigates the delamination"
• Context and Importance: This functional language is the core of Claim 1. The definition of "mitigates" will be critical to determining infringement. Practitioners may focus on whether this requires completely stopping delamination growth or merely reducing its rate or effect, and whether the mitigation must be the intended purpose of the structure.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification describes the barrier as an "efficient barrier for the growth of delamination," which may suggest that its function is to impede or slow, not necessarily halt, the process ('611 Patent, col. 2:23-24).
  • Evidence for a Narrower Interpretation: The problem statement focuses on preventing "crack or tear off the bondwire" ('611 Patent, col. 1:49-50). This context could support an argument that "mitigates" should be construed to mean preventing the specific delamination that would otherwise cause bondwire failure.

Term from the ’299 Patent: "temporary carrier"

• The Term: "temporary carrier"
• Context and Importance: The claimed method begins by mounting die onto a "temporary carrier." The scope of this term is central, as it defines the starting workpiece for the patented process. The dispute may focus on whether any substrate used during manufacturing that is later removed qualifies, or if the term implies specific characteristics.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim language itself is broad and does not specify the material or nature of the carrier.
  • Evidence for a Narrower Interpretation: The detailed description provides a specific example of a "two-sided adhesive carrier tape, REVALPHA® tape" mounted in a "carrier ring apparatus" ('299 Patent, col. 4:10-12). A defendant may argue that the term should be construed in light of this embodiment to mean a flexible, adhesive film system, not just any rigid or temporary substrate.

VI. Other Allegations

• Indirect Infringement: For all asserted patents, the complaint alleges induced infringement, stating Defendant knowingly and intentionally induces infringement by third parties such as "semiconductor foundries, ... manufacturers, customers, and/or end-users" (Compl. ¶¶40, 60, 78, 96). For the '299 and '837 method patents, the complaint also alleges infringement by importing products made by the patented process (Compl. ¶¶63, 81).
• Willful Infringement: The complaint does not use the term "willful," but alleges that Defendant possessed knowledge of infringement "at least as of the date of this Complaint" (Compl. ¶¶41, 61, 79, 97). It also alleges that Defendant acted with the belief of a high probability of infringement "while remaining willfully blind," which could support a claim for post-suit willful infringement (Compl. ¶¶42, 62, 80, 98). No allegations of pre-suit knowledge are made.

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of process evidence: For the method claims in the '299 and '837 Patents, can the plaintiff obtain sufficient evidence through discovery and reverse engineering to prove that the defendant's confidential, non-public manufacturing processes perform the specific steps recited in the claims?
• A second issue will be one of functional scope: For the '611 Patent, the case may turn on claim construction. Can the term "mitigates the delamination" be defined with sufficient clarity, and does the accused product's physical structure, as-designed and as-manufactured, actually perform this function?
• A third key question will be one of structural identity: For the '189 Patent, does the accused product’s "power rail pad" meet the claim requirement of being a "non-circuit node," a technical distinction that will likely require expert testimony to resolve? The complaint supports this with a circuit diagram from the product datasheet (Compl. p. 37).