Everlight Electronics Co Ltd v. Seoul Semiconductor Co Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Everlight Electronics Co., Ltd. (Taiwan)
  • Defendant: Seoul Semiconductor Co., Ltd. (Republic of Korea)
  • Plaintiff’s Counsel: Venable LLP; Miller Fair Henry PLLC
• Case Identification: 2:26-cv-00119, E.D. Tex., 02/13/2026
• Venue Allegations: Plaintiff alleges venue is proper because Defendant is a foreign corporation subject to jurisdiction in the district, has transacted business there, and has committed acts of patent infringement in the district. The complaint also notes that Defendant has previously invoked the court's jurisdiction in other lawsuits, suggesting purposeful availment.
• Core Dispute: Plaintiff alleges that Defendant’s LED products, which are imported into and sold in the U.S., are manufactured using a process that infringes a patent related to the structure and manufacturing of semiconductor light-emitting elements.
• Technical Context: The lawsuit concerns the manufacturing process for light-emitting diodes (LEDs), specifically methods for constructing the electrical contacts on the LED chip to facilitate reliable, large-scale mounting onto circuit boards.
• Key Procedural History: The complaint notes that Defendant has previously filed lawsuits in the Eastern District of Texas, which Plaintiff may use to argue that Defendant has purposefully availed itself of the benefits and protections of Texas law, supporting personal jurisdiction and venue.

Case Timeline

Date	Event
2004-09-27	’126 Patent Priority Date
2005-09-22	’126 Patent PCT Filing Date
2009-06-30	’126 Patent Issue Date
2026-02-13	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,554,126 - Semiconductor Light-Emitting Element, Manufacturing Method and Mounting Method of the Same and Light-Emitting Device

The Invention Explained

• Problem Addressed: The patent describes challenges in mounting large-format LED chips onto circuit boards (’126 Patent, col. 2:1-6). Conventional methods required high-precision "flip chip" mounting using small bumps, because the area for the negative electrical contact (the n-electrode) was small (’126 Patent, col. 2:26-40). This process was difficult, required high precision, and could lower production efficiency and yield, especially when using common, low-cost bonding materials like solder (’126 Patent, col. 2:26-40).
• The Patented Solution: The invention proposes a new layered structure for an LED chip that creates larger external electrical contacts, making them easier to mount (’126 Patent, abstract). The process involves forming initial, smaller electrodes (a "first n-electrode" and "first p-electrode") on the semiconductor layers, covering them with an insulating layer, and then forming larger, external electrodes (a "second n-electrode" and "second p-electrode") on top of the insulating layer (’126 Patent, abstract; ’126 Patent, col. 7:16-24). The key innovation is that the second n-electrode is larger than the underlying first n-electrode, providing a bigger target for mounting with solder and thus simplifying manufacturing (’126 Patent, col. 3:5-13; ’126 Patent, Fig. 1).
• Technical Importance: This approach allows for the use of low-cost, conventional mounting techniques like soldering for even large-format, high-power LEDs, which could improve production efficiency and reduce manufacturing costs (’126 Patent, col. 2:41-50; Compl. ¶11).

Key Claims at a Glance

• The complaint asserts method claims, with Claim 9 identified as exemplary (Compl. ¶¶12, 14).
• Independent Claim 9 recites the following essential method steps:
  • Preparing a bare light-emitting element with n-type and p-type semiconductor layers and first n- and p-electrodes.
  • Forming a first insulating layer to insulate the first n-electrode and first p-electrode from each other.
  • Forming a second n-electrode on the first n-electrode and insulating layer, where the second n-electrode has an area larger than the joined face between the n-type semiconductor and the first n-electrode, and is electrically connected to the first n-electrode.
  • Forming a second p-electrode on the first p-electrode, where the second p-electrode has an area smaller than the joined face between the n-type semiconductor layer and the p-type semiconductor layer, and is electrically connected to the first p-electrode.
• The complaint does not explicitly reserve the right to assert dependent claims, but states that the accused products infringe "one or more method claims" (Compl. ¶13).

III. The Accused Instrumentality

Product Identification

The complaint identifies Defendant’s "WICOP HF Series modules," including the "SWW0CS10A module" (Compl. ¶13). These products are allegedly incorporated into automobiles (Compl. ¶13).

Functionality and Market Context

The complaint describes the accused products as "light emitting products" (Compl. ¶13). The infringement allegation is not based on the function of the final product, but rather on the process by which the LED components within them are manufactured (Compl. ¶¶13-14). The complaint asserts that these products are made by a process covered by the ’126 Patent and are then imported into, offered for sale, sold, or used within the United States (Compl. ¶13).

IV. Analysis of Infringement Allegations

The complaint references an exemplary claim chart attached as Exhibit 2, but this exhibit was not included with the filing (Compl. ¶14). The complaint’s narrative infringement theory alleges that Defendant manufactures the Accused Products using a process that practices every step of at least Claim 9 of the ’126 Patent (Compl. ¶¶13-14). The allegations are directed at infringement under 35 U.S.C. § 271(g), which prohibits the importation, sale, or use of a product made by a process patented in the United States (Compl. ¶13). The complaint does not provide specific factual details mapping the steps of Seoul Semiconductor’s manufacturing process to the claim elements.

No probative visual evidence provided in complaint.

• Identified Points of Contention:
  • Factual Question: The central dispute will be factual: does the specific, proprietary process used by Seoul Semiconductor to manufacture its WICOP HF Series modules include all the steps recited in Claim 9 of the ’126 Patent? This will require discovery into Defendant's manufacturing methods.
  • Scope Questions: The analysis may turn on the interpretation of the claim’s size requirements. For example, what is the scope of "an area larger than a joined face between the n-type semiconductor and the first n-electrode" and "an area smaller than a joined face between the n-type semiconductor layer and the p-type semiconductor layer"? The parties may dispute the precise definition of the "joined face" and the methodology for comparing these areas.

V. Key Claim Terms for Construction

• The Term: "a first insulating layer so as to insulate the first n-electrode and the first p-electrode from each other" (from Claim 9).

• Context and Importance: The structure and function of this insulating layer are central to the claimed invention, as it enables the creation of the larger, overlying second electrodes without causing a short circuit. The dispute may focus on what degree of "insulation" is required and whether any intervening layers or materials in the accused process perform this function as claimed.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The claim language itself is functional, requiring insulation without specifying a particular material or complete encapsulation. This may support an argument that any layer preventing electrical connection between the first electrodes meets the limitation.
  • Evidence for a Narrower Interpretation: The specification describes the insulating layer as being "formed by an oxide film, a nitride film or the like of silicon" (’126 Patent, col. 7:59-61). An accused infringer might argue this description limits the scope of insulating materials to those explicitly disclosed or their direct equivalents.

• The Term: "an area larger than a joined face" and "an area smaller than a joined face" (from Claim 9).

• Context and Importance: These relative size limitations are the core of the claimed structural improvement, as they define the creation of a large n-electrode for easier mounting. The case could hinge on how the "joined face" is defined and how the "area" is measured, particularly if the shapes are irregular.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patent’s stated goal is to create a larger mounting area for the n-electrode to facilitate solder bonding (’126 Patent, col. 6:49-55). A patentee may argue that any configuration achieving this functional goal should be considered "larger," regardless of the precise measurement methodology.
  • Evidence for a Narrower Interpretation: The figures provide specific geometric arrangements, such as isosceles triangles (’126 Patent, col. 8:1-5; ’126 Patent, Fig. 2). A defendant could argue these embodiments suggest a more constrained interpretation of how the areas are defined and compared.

VI. Other Allegations

• Indirect Infringement: The complaint primarily focuses on infringement under 35 U.S.C. § 271(g) for importing products made by a patented process (Compl. ¶13). It makes a general allegation of infringement under 35 U.S.C. § 271 but does not plead specific facts to support theories of induced or contributory infringement (Compl. ¶13).
• Willful Infringement: The complaint alleges that Defendant has had knowledge of the ’126 Patent and its infringement "at least as of the service of this Complaint" (Compl. ¶16). It further reserves the right to seek enhanced damages for willfulness based on any pre-suit knowledge uncovered during discovery or for any infringing conduct that continues post-filing (Compl. ¶16).

VII. Analyst’s Conclusion: Key Questions for the Case

1. A Primary Evidentiary Question: The case will fundamentally depend on evidence obtained in discovery. The key question is: What are the specific steps in Seoul Semiconductor's manufacturing process for its WICOP HF series LEDs, and is there evidence that this process directly corresponds to each limitation of the asserted method claims, particularly the formation of distinct "first" and "second" electrodes separated by an insulating layer with the claimed relative sizes?
2. A Question of Claim Construction: The dispute will likely involve claim construction, focusing on the relative size limitations. A core issue will be one of definitional scope: how should the court define the term "joined face," and what is the proper method for comparing its "area" to that of the second electrodes, especially if the components have complex, non-uniform geometries?
3. A Jurisdictional and Venue Question: Given that both parties are foreign corporations, an early point of contention may be personal jurisdiction and venue in the Eastern District of Texas. The question will be whether Defendant’s sales and activities in the district, combined with its history of filing suits there, are sufficient to establish proper venue over Plaintiff’s claims.