DCT

2:26-cv-00032

Mr Licensing LLC v. Renesas Electronics Corp

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:26-cv-00032, E.D. Tex., 01/13/2026
  • Venue Allegations: Venue is asserted on the basis that the Defendant is a foreign corporation that may be sued in any judicial district and has allegedly committed acts of infringement, transacted business, and placed products into the stream of commerce within the Eastern District of Texas.
  • Core Dispute: Plaintiff alleges that Defendant's Renesas RL78 family of microcontrollers infringes three patents related to semiconductor memory protection, power management, and watchdog timer functionality.
  • Technical Context: The technology at issue pertains to power-saving and security features in low-power microcontrollers, which are fundamental components in a wide array of embedded electronic devices.
  • Key Procedural History: The complaint alleges that the patents' previous owner, Monterey Research, LLC, engaged in "extensive communications" with Renesas regarding its patent portfolio and that Renesas requested Monterey to "cease informing it" of the patents, which forms the basis for a willfulness allegation.

Case Timeline

Date Event
2006-01-31 '664 Patent Priority Date
2006-12-22 '477 Patent Priority Date
2009-06-30 U.S. Patent No. 7,555,664 Issued
2009-07-21 U.S. Patent No. 7,565,477 Issued
2009-08-26 '911 Patent Priority Date
2015-03-10 U.S. Patent No. 8,977,911 Issued
2020-01 Alleged Infringement Start Date
2026-01-13 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,565,477

  • Patent Identification: U.S. Patent No. 7,565,477, "Semiconductor device and method of controlling the same," issued July 21, 2009. Compl. ¶7
  • The Invention Explained:
    • Problem Addressed: The patent's background describes the challenge of providing robust and flexible write-protection for different memory regions in a semiconductor device, noting that prior art methods could be inflexible or require large circuit areas. '477 Patent, col. 2:35-52
    • The Patented Solution: The invention proposes a hierarchical memory protection scheme. It uses "first program disabling information" for granular, region-by-region control over programmability. It adds a "collective program disabling information" mechanism that can act as a master override. A "program disabling information selection circuit" determines the final programming status, prioritizing the collective command to disable programming across all regions when it is active, but otherwise deferring to the individual region settings. '477 Patent, abstract '477 Patent, FIG. 2
    • Technical Importance: This design allows for both fine-grained control over specific memory areas and a high-level security override, offering a more flexible and area-efficient approach to memory protection than prior methods. '477 Patent, col. 4:5-15
  • Key Claims at a Glance:
    • The complaint asserts at least independent claim 1. Compl. ¶20
    • Independent Claim 1 is a system claim requiring:
      • A plurality of memory regions with non-volatile memory cells.
      • A plurality of "disabling information memory units," one for each region, storing "first program disabling information" (i.e., individual enable/disable settings).
      • A "program disabling information selection circuit" that outputs "second program disabling information." This circuit outputs a "disable" command if a "collective program disabling" command is active, regardless of the individual settings. If the collective command is not active, it outputs the individual setting.
      • A "program control circuit" that disables or enables programming for a region based on the output of the selection circuit.

U.S. Patent No. 7,555,664

  • Patent Identification: U.S. Patent No. 7,555,664, "Independent control of core system blocks for power optimization," issued June 30, 2009. Compl. ¶8
  • The Invention Explained:
    • Problem Addressed: The patent's background explains that microcontrollers typically offer a small number of predefined, device-wide power-saving modes. These modes are not customizable by programmers and do not allow for independent power control of specific internal circuits, known as "core system blocks." '664 Patent, col. 1:13-21
    • The Patented Solution: The invention describes a power management unit that can independently control individual core system blocks. It introduces the concept of "sampling," where a core system block is periodically powered on to perform its function and then powered off to conserve energy. This process is configurable by an application programmer, allowing for customized power optimization even while the main processor is in a sleep state. '664 Patent, abstract '664 Patent, col. 2:36-43
    • Technical Importance: This technology enables more granular and efficient power management in processing devices, with certain embodiments providing reduced average power consumption. '664 Patent, col. 3:23-26
  • Key Claims at a Glance:
    • The complaint asserts at least independent claim 1. Compl. ¶37
    • Independent Claim 1 is a method claim requiring:
      • Providing power management commands to a power management unit that is coupled to a "core system block," where the commands are provided under the control of a processor.
      • Sampling the "core system block" under the control of the power management unit, where sampling includes "periodically powering the core system block while the processor is in a sleep mode."

Multi-Patent Capsule: U.S. Patent No. 8,977,911

  • Patent Identification: U.S. Patent No. 8,977,911, "Watchdog timer with mode dependent time out," issued March 10, 2015. Compl. ¶9
  • Technology Synopsis: The patent addresses an issue with watchdog timers in systems that have multiple power or frequency modes. A fixed watchdog timeout suitable for a high-speed mode may be too short for a low-power mode, causing erroneous system resets. The invention is a method and apparatus where the watchdog timer's timeout value is automatically changed in response to a change in the processing system's mode of operation. '911 Patent, abstract '911 Patent, col. 1:40-51
  • Asserted Claims: The complaint asserts at least independent claim 1. Compl. ¶49
  • Accused Features: The complaint alleges that the watchdog timer in the Renesas RL78/G23 microcontrollers infringes by having its timeout value and counting operation change in response to the device transitioning between normal operation and low-power modes such as HALT, STOP, or SNOOZE. Compl. ¶¶50-52

III. The Accused Instrumentality

  • Product Identification: The complaint accuses "all versions and variants of the Renesas RL78 microcontroller since January of 2020," with specific examples including the RL78/G23 and RL78/G13 models. Compl. ¶12 Compl. ¶21 Compl. ¶38
  • Functionality and Market Context: The Renesas RL78 family is described as a line of low-power, energy-efficient microcontrollers intended for compact systems. Compl. ¶21 The complaint focuses on specific technical features:
    • Memory Protection: The RL78 products include a "FLASH Shield Window Function," which uses FSWS and FSWE registers to define protected memory areas, as well as separate control bits (BTPR, DFLEN) for protecting the boot and data flash areas. A master control register (FLPMC) is alleged to provide a collective override for these settings. Compl. ¶¶23-28 The complaint includes a diagram from the accused product's user manual that illustrates how the "Flash shield area" protects memory blocks from self-programming. Compl. ¶23, p. 9
    • Power Management: The products feature HALT, STOP, and SNOOZE power modes. The SNOOZE mode is specifically identified as an infringing feature, wherein the microcontroller enters a low-power STOP state, but can periodically wake up certain peripherals (e.g., an A/D converter, serial interface) to perform tasks without waking the main CPU, thereby saving power. Compl. ¶¶38-40 The complaint presents a state diagram of the accused product's low power modes, showing the relationships between Operating, Halt, Stop, and Snooze states. Compl. ¶39, p. 23
    • Watchdog Timer: The RL78 products include a watchdog timer whose operation is allegedly altered when the device enters a low-power mode like HALT or STOP, effectively changing its timeout period. Compl. ¶¶50-52

IV. Analysis of Infringement Allegations

'477 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a plurality of memory regions that include non-volatile memory cells; The RL78 Accused Products include multiple non-volatile code and data memory regions comprised of FLASH memory cells. ¶22 col. 9:56-60
a plurality of disabling information memory units...storing first program disabling information... The RL78 products include FSWS/FSWE registers, a BTPR bit, and a DFLEN bit that function as memory units storing start/end addresses or flags that indicate whether programming is disabled for corresponding memory regions. ¶¶23-25 col. 9:60-65
a program disabling information selection circuit that outputs second program disabling information...when programming is disabled collectively...outputting the first program disabling information...when programming is not collectively disabled; The FLPMC register in RL78 products contains bits (FWEDIS, FLSPM, EEEMD) that allegedly function as a collective override. When set, they disable programming for entire memory areas regardless of the individual settings in the FSWS/BTPR/DFLEN units. When not set, the individual settings control access. This logic inherently performs the claimed selection function. ¶¶26-28 col. 10:4-15
a program control circuit that disables or enables programming in the corresponding memory region in accordance with the second program disabling information. The complaint alleges that the logic circuitry in the RL78 products that implements the final enable/disable decision based on the output of the aforementioned selection logic constitutes the claimed program control circuit. ¶¶27-28 col. 10:11-14
  • Identified Points of Contention:
    • Structural Question: A central issue may be whether the accused product's combination of distributed registers and control bits (FLPMC, FWEDIS, etc.) constitutes the claimed "program disabling information selection circuit". The patent depicts this element as a discrete logic block '477 Patent, FIG. 2, item 44, raising the question of whether the allegedly inherent and distributed functionality of the accused device meets this structural limitation.
    • Scope Question: The analysis may focus on whether the various accused registers (FSWS/FSWE, BTPR bit, DFLEN bit) are properly characterized as a "plurality of disabling information memory units" that "correspond to the memory regions" in the manner required by the claim.

'664 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
providing power management commands to a power management unit of a processing device... under control of a processor... The RL78 products practice a method where software instructions (commands) executed by the CPU invoke HALT, STOP, and SNOOZE modes, which are managed by a power management unit (e.g., clock generator, standby controller). ¶¶38-39 col. 2:44-49
sampling the core system block under control of the power management unit... In SNOOZE mode, the power management unit of the RL78 products wakes up peripheral devices like the A/D converter or serial interfaces (UART, CSI) to perform functions. ¶40 col. 3:21-23
wherein sampling includes periodically powering the core system block while the processor is in a sleep mode. The SNOOZE mode is entered from the STOP mode, where the CPU is stopped (in a sleep mode). While the CPU remains stopped, peripherals are periodically powered to perform tasks (e.g., A/D conversion, data receipt) before the system returns to the STOP mode to await the next trigger. ¶40 col. 2:40-43
  • Identified Points of Contention:
    • Definitional Scope: A primary point of contention will likely be whether the accused peripherals (A/D converter, UART, CSI) qualify as a "core system block" as that term is used in the patent. The patent's specification provides examples such as "a power supply monitor, a voltage reference, a voltage regulator" and distinguishes them from "application level blocks." '664 Patent, col. 2:23-25 '664 Patent, col. 2:34-36 The case may turn on whether the accused peripherals fall within the patent's definition.
    • Technical Question: The analysis will question whether the operation of the SNOOZE mode constitutes "periodically powering" the block. The defense may argue the block is not fully powered down and back up, but rather transitions between different clocking or activity states, raising a factual question about the nature of the power cycling.

V. Key Claim Terms for Construction

For the '664 Patent:

  • The Term: "core system block"
  • Context and Importance: This term is critical because the infringement allegation for the '664 Patent hinges on classifying the accused product's peripherals (A/D converter, UART interfaces) as "core system blocks". The patent's distinction between "core system blocks" and "application level blocks" makes the construction of this term central to the dispute.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification states that a core system block "includes an analog device" and that they "provide support to the application level blocks." '664 Patent, col. 2:32-33 Plaintiff may argue that an A/D converter is an analog device that provides support to applications, fitting this description.
    • Evidence for a Narrower Interpretation: The specification provides a specific, seemingly limiting list of examples: "a power supply monitor, a voltage reference, a voltage regulator, or the like." '664 Patent, col. 2:34-36 Defendant may argue that this list confines the term's scope to fundamental, system-level power and reference circuits, excluding the application-focused I/O peripherals accused of infringement.

For the '477 Patent:

  • The Term: "program disabling information selection circuit"
  • Context and Importance: Practitioners may focus on this term because the complaint maps this claimed circuit to a collection of distributed logic bits and registers in the accused product, rather than a single, discrete component. The construction will determine whether this "inherent functionality" meets the structural requirement of the claim.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claim language is primarily functional, describing what the circuit "outputs" in response to certain inputs. Plaintiff may argue that any combination of hardware that performs this precise logical function meets the limitation, regardless of whether it is a single, unified block.
    • Evidence for a Narrower Interpretation: The patent's figures and detailed description depict the "program disabling information selection circuit" as a distinct structural element (item 44 in FIG. 2) that receives specific inputs. Defendant may argue this disclosure implies a more specific and unified structure than the distributed logic found in the accused product.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement of infringement for all asserted patents, based on Defendant manufacturing and selling the Accused Products along with "technical support, marketing, product manuals, advertisements, and online documentation" that instruct and encourage end-users to use the accused memory protection and power-saving features in an infringing manner. Compl. ¶29 Compl. ¶41 Compl. ¶54 The complaint separately pleads contributory infringement under 35 U.S.C. § 271(c) for each asserted patent, alleging that the accused components within the Accused Products are material to the claimed inventions, are not staple articles or commodities of commerce suitable for substantial non-infringing use, and are especially made or adapted for infringing use. Compl. ¶42 Compl. ¶55
  • Willful Infringement: Willfulness is alleged for all asserted patents. The complaint pleads that Renesas either had pre-suit knowledge of the patents or was willfully blind to them, with the pleaded predicate being deliberate avoidance: during "extensive communications" with the patents' prior owner, Monterey Research, LLC, Renesas allegedly requested that Monterey "cease informing it" of the patents and took "affirmative steps to avoid learning" about its infringement. Compl. ¶¶13-15 Compl. ¶31 Compl. ¶43 Compl. ¶56

VII. Analyst's Conclusion: Key Questions for the Case

  1. A Definitional Scope Question: A core issue for the '664 Patent will be whether the term "core system block", which the patent illustrates with examples like voltage regulators and power monitors, can be construed to cover the application-level peripherals (A/D converter, UART) that are periodically activated in the accused product's "Snooze" mode.
  2. A Structural Equivalence Question: The '477 Patent analysis will likely focus on whether the claimed "program disabling information selection circuit", depicted as a discrete logic element in the patent, is met by the accused product's distributed system of registers and control bits, raising a fundamental question of structural correspondence versus functional equivalency.
  3. An Evidentiary Question of Knowledge: The willfulness inquiry will turn on evidence related to the alleged "extensive communications" between Defendant and the prior patent owner. The key question for the court will be what these communications contained and whether they establish pre-suit knowledge of infringement or, alternatively, a deliberate avoidance of such knowledge.
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