Palisade Tech LLP v. Yangtze Memory Tech Co Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:

  • Plaintiff: Palisade Technologies, LLP (Nevada)
  • Defendant: Yangtze Memory Technologies Company, Ltd. (China)
  • Plaintiff's Counsel: Nelson Bumgardner Conroy PC

• Case Identification: 2:25-cv-01170, E.D. Tex., 04/07/2026

• Venue Allegations: Venue is alleged based on Defendant being a foreign entity, which may be sued in any judicial district under 28 U.S.C. § 1391(c)(3). The complaint further alleges Defendant has substantial business ties to the district, including placing accused products into the stream of commerce.

• Core Dispute: Plaintiff alleges that Defendant's 3D NAND flash memory devices infringe five U.S. patents related to semiconductor memory architecture, operation, and manufacturing methods.

• Technical Context: The technology at issue is 3D NAND flash memory, which achieves high storage densities by stacking memory cells vertically and is a foundational component in modern data storage, from consumer electronics to enterprise data centers.

• Key Procedural History: The complaint notes that Defendant, YMTC, previously filed a patent infringement suit against Micron Technology, Inc. in the same court on October 6, 2025. Plaintiff Palisade states it provided notice of infringement to Defendant via its original complaint filed on November 26, 2025, and served detailed infringement contentions on March 12, 2026.

Case Timeline

Date	Event
2007-01-31	'329 Patent Priority Date
2010-04-13	'329 Patent Issued
2010-09-30	'853 Patent Priority Date
2013-05-14	'853 Patent Issued
2014-05-08	'838 Patent Priority Date
2014-10-10	'314 Patent Priority Date
2015-03-31	'838 Patent Issued
2015-07-22	'974 Patent Priority Date
2016-03-08	'314 Patent Issued
2016-12-20	'974 Patent Issued
2025-10-06	Defendant YMTC files suit against Micron
2025-11-26	Plaintiff files original complaint
2026-03-12	Plaintiff serves infringement contentions
2026-04-07	Plaintiff files First Amended Complaint

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,697,329 - "Methods and Apparatus for Using a Configuration Array Similar to an Associated Data Array"

The Invention Explained

• Problem Addressed: The patent's background explains that memory devices often use a small "configuration array" to store parameters for operating the main, much larger "data array" U.S. Patent No. 7,697,329, col. 4:1-5 Because these two arrays have different primary design goals (e.g., robustness for the configuration array vs. density for the data array), they are often designed with different physical layouts and orientations on the semiconductor substrate '329 Patent, col. 4:19-35 This divergence creates a manufacturing problem: a process adjustment intended to improve the data array's yield might inadvertently harm the differently-oriented configuration array, and vice versa '329 Patent, col. 5:1-12
• The Patented Solution: The invention proposes to solve this problem by designing the configuration array to be "substantially similar" to the data array, particularly by disposing both on the substrate in the "same orientation" '329 Patent, abstract '329 Patent, col. 5:50-55 This includes aligning their respective wordlines and bitlines to run in the same directions and can extend to making other features, such as driver layouts and the relative locations of "zia contact regions," substantially similar as well '329 Patent, col. 8:5-20 By ensuring both arrays share a common physical layout, they will react to manufacturing process variations in a similar manner, which is intended to improve overall device reliability and yield '329 Patent, col. 5:51-55
• Technical Importance: This design principle simplifies process control during high-volume semiconductor manufacturing by ensuring that optimizations applied across the wafer have a consistent effect on both the user data storage areas and the critical configuration storage areas.

Key Claims at a Glance

• The complaint asserts independent Claim 1 Compl. ¶29
• The essential elements of Claim 1 are:
  • A memory comprising a substrate with a data array and a separate configuration array for storing configuration information for the data array.
  • The configuration array and data array are disposed on the substrate in a "same orientation" relative to each other.
  • The configuration array includes a plurality of "zia contact regions" disposed in "substantially similar relative locations" as a plurality of zia contact regions in the data array.
• The complaint expressly reserves the right to assert additional claims Compl. ¶29, n.1

U.S. Patent No. 8,441,853 - "Sensing for NAND Memory Based on Word Line Position"

The Invention Explained

• Problem Addressed: In a NAND flash memory string, the electrical characteristics of a memory cell are affected by its physical position. Specifically, cells near the "drain side" of the string are typically programmed after cells on the "source side." This programming order creates a "back pattern effect," where the already-programmed source-side cells present a higher resistance, causing a shift and widening of the threshold voltage (Vth) distributions for the drain-side cells U.S. Patent No. 8,441,853, col. 3:10-25 This variability makes it difficult to reliably read data, especially in multi-level cell (MLC) devices that rely on narrow, distinct Vth windows.
• The Patented Solution: The patent discloses a method to compensate for this position-based variation by adjusting the sensing operation based on the cell's location within the NAND string '853 Patent, abstract The invention proposes assigning the memory cells (and their corresponding word lines) into multiple "groups" based on their position '853 Patent, col. 9:5-9 The sensing process is then "adjusted" differently for each group. The patent suggests making the group closest to the source side the largest, as these cells are less affected by the back-pattern effect and can be treated uniformly, while other smaller groups closer to the drain receive more tailored adjustments '853 Patent, col. 9:20-35 The adjustment can involve modifying parameters such as body bias, source voltage, or sensing time during a read or verify operation '853 Patent, col. 4:32-37
• Technical Importance: This method improves the read margins and overall reliability of NAND flash memory by actively compensating for predictable, position-dependent electrical variations, a critical step for enabling higher-density storage.

Key Claims at a Glance

• The complaint asserts independent Claim 1, a method claim Compl. ¶52
• The essential elements of Claim 1 are:
  • Assigning each non-volatile storage element of a NAND string to one of multiple groups of different sizes.
  • The group closest to the source side has more storage elements than any other group.
  • Connecting the NAND string at its drain side to a bit line and sensing circuitry.
  • Sensing the threshold voltage of a selected element, where the "sensing is adjusted based on a position of the one group" to which the element is assigned.
• The complaint expressly reserves the right to assert additional claims Compl. ¶29, n.1

U.S. Patent No. 8,996,838 - "Structure Variation Detection for a Memory Having a Three-Dimensional Memory Configuration"

• Technology Synopsis: This patent addresses physical variations, such as the "tapering" of vertical structures, that can occur during the fabrication of 3D memories '838 Patent, abstract '838 Patent, col. 2:1-10 The invention describes a method for a data storage device to store information that identifies the location of such a structural variation and to subsequently access that information, which can then be used to modify memory operations to compensate for the effects of the variation '838 Patent, abstract
• Asserted Claims: Independent Claim 1 Compl. ¶73
• Accused Features: The complaint alleges that YMTC's 3D NAND products comprise a 3D memory with a structure extending through multiple layers, store information identifying a location of variation in that structure, and access this information to determine finely tuned programming voltages Compl. ¶¶73-75

U.S. Patent No. 9,281,314 - "Non-Volatile Storage Having Oxide/Nitride Sidewall"

• Technology Synopsis: This patent describes a method for manufacturing a non-volatile memory device with a specific sidewall structure to improve electrical isolation and performance '314 Patent, abstract The method involves forming lines of memory cells, covering the sidewalls of both the charge storage regions and word lines with oxide, and then forming a nitride region that covers only the oxide adjacent to the word lines, leaving the oxide next to the charge storage regions exposed '314 Patent, col. 2:4-9 This structure is intended to protect the word lines during manufacturing without introducing charge-trapping nitride material near the charge storage region, which could degrade device performance.
• Asserted Claims: Independent Claim 13 Compl. ¶89
• Accused Features: The complaint alleges that the method used to manufacture YMTC's accused products infringes by forming lines of memory cells, word lines, and then using a sequence of first oxide regions, second oxide regions, and nitride regions to create the claimed isolation structure Compl. ¶¶91-95

U.S. Patent No. 9,524,974 - "Alternating Sidewall Assisted Patterning"

• Technology Synopsis: This patent relates to a semiconductor manufacturing process known as sidewall assisted patterning (SAP), used to create features smaller than what is possible with conventional photolithography. The invention is a method for creating trenches with two different, alternating cross-sectional profiles '974 Patent, abstract For example, one set of trenches may be formed with a wider top portion to facilitate connections, while the alternating set of trenches is more uniform. This technique can be used to create alternating structures, such as conductive bit lines interspersed with air gaps for improved electrical isolation '974 Patent, col. 2:14-20
• Asserted Claims: Independent Claim 17 Compl. ¶109
• Accused Features: The complaint alleges that YMTC's manufacturing process uses a double patterning technology that infringes the claimed method. The allegations describe a process of forming mandrels, depositing a liner layer and sidewall spacers, removing the mandrels, and then etching a pattern of "first trenches" and "second trenches" with different shapes to form bit lines Compl. ¶¶111-117

III. The Accused Instrumentality

Product Identification

• The accused instrumentalities are "certain semiconductor memory devices, including NAND flash memory devices" manufactured, used, sold, or imported by Defendant YMTC Compl. ¶2 A specific exemplary product identified is a 3D NAND memory device, part number YMN0ATF1B1HPAD, which was found inside a KingSpec XG7000 solid-state drive (SSD) Compl. ¶¶26-27

Functionality and Market Context

• The accused products are 3D NAND flash memory chips, a form of non-volatile data storage Compl. ¶10 The complaint alleges these devices are widely used in mobile devices, consumer electronics, computers, and data centers Compl. ¶10 The complaint cites a third-party source and YMTC's own statements in other litigation to position YMTC as "the leader in 3D NAND flash" with a "leadership role in the NAND market" Compl. ¶11 It is also alleged that YMTC targets the U.S. market directly and through its U.S. subsidiary, YMTI, for sales, marketing, testing, and customer support Compl. ¶¶12-15 The complaint provides a teardown photograph of a packaged YMTC 3D NAND chip with the specific part number YMN0ATF1B1HPAD Compl. ¶27

IV. Analysis of Infringement Allegations

'329 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a memory comprising: a substrate including: a data array; and a configuration array associated with, but separate from, the data array and adapted to store configuration information for configuring the data array...	The accused products are a memory that includes a substrate, a main data array for user data, and a separate configuration array that stores configuration information for the data array, such as the parameters shown in YMTC's product datasheets. The complaint shows a die photograph identifying the data array area Compl. ¶31	¶31; ¶32	col. 5:13-20
wherein the configuration array and the data array are disposed on the substrate in a same orientation as each other relative to the substrate...	The accused products allegedly have a single memory cell orientation across the device, as shown in a die photograph, meaning the configuration array and data array are disposed in the same orientation relative to the substrate Compl. ¶35	¶35	col. 8:41-43
and wherein the configuration array includes a plurality of zia contact regions that are disposed in substantially similar relative locations in the configuration array as a plurality of zia contact regions disposed in the data array.	The accused products allegedly include "zia structures," and because the cell orientation is consistent throughout the device, the zia region is the same for both the configuration array and the data array Compl. ¶36 The complaint provides an SEM image labeled "Zia" to support this allegation Compl. p. 17	¶36	col. 8:44-49

• Identified Points of Contention:
  • Scope Questions: A potential dispute may arise over the term "same orientation." The analysis may question whether the mere geometric alignment of wordlines and bitlines, as alleged, is sufficient to meet this limitation, or if the patent requires a more comprehensive similarity in the layout of associated circuits (e.g., drivers, decoders) which may differ between the data and configuration arrays.
  • Technical Questions: The complaint's assertion that the configuration array and data array share "substantially similar" zia contact regions because the overall cell orientation is consistent raises an evidentiary question. It is an open question what evidence demonstrates that the structures identified as "zia" contacts in the configuration part of the memory are located in relatively the same positions as those in the main data array, as required by the claim.

'853 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a method for sensing a selected non-volatile storage element in a NAND string which comprises non-volatile storage elements connected in series, and which has a source side and a drain side.	The accused products are 3D NAND memory containing NAND strings with non-volatile storage elements, a source side, and a drain side, as illustrated in an annotated image of the device structure Compl. ¶52	¶52	col. 3:7-10
assigning each non-volatile storage element...to a group among multiple groups...the multiple groups have different sizes, and a group...which is closest to the source side has more non-volatile storage elements...than any other group of the multiple groups.	The storage elements in the accused products are allegedly assigned to groups of different sizes, specifically a "source side deck" with 128 wordlines and a "drain side deck" with 125 wordlines. The source side deck is identified as being closest to the common source plate and containing more storage elements (wordlines) than the drain side deck Compl. ¶53 Compl. ¶54 An annotated image illustrates this deck structure Compl. ¶54	¶53; ¶54	col. 18:8-13
...sensing whether a threshold voltage of the selected non-volatile storage element is above a control gate voltage using the sensing circuitry, the sensing is adjusted based on a position of the one group in the NAND string.	The complaint alleges the sensing operation is adjusted based on the element's group position. It cites a separate YMTC patent ('671 patent) as evidence that YMTC uses a process to set maximum pass voltages based on the structural position and vulnerability of memory cells to "pass disturb," which varies by location Compl. ¶56 This process is alleged to be the claimed "adjustment."	¶56	col. 18:18-21

• Identified Points of Contention:
  • Scope Questions: The infringement theory relies on equating a process described in a separate YMTC patent (setting pass voltages to mitigate "pass disturb") with the claimed step of "sensing is adjusted based on a position." This raises the question of whether adjusting a programming parameter (pass voltage) for one purpose (mitigating pass disturb) falls within the scope of adjusting a sensing operation for the purpose described in the '853 patent (compensating for the back pattern effect).
  • Technical Questions: The central evidentiary question is whether the accused products actually perform the claimed adjustment. The complaint infers the method from the device's physical structure and descriptions in other YMTC patents. It remains an open question what direct evidence shows that the accused devices modify their sensing operation (e.g., body bias, sensing time, pre-charge level) in a manner that is dependent on which "deck" or group a memory cell belongs to.

V. Key Claim Terms for Construction

For the '329 Patent

• The Term: "same orientation"
• Context and Importance: This term is central to the patent's proposed solution for improving manufacturing yield. The infringement allegation hinges on the observation that the accused die has a uniform layout of memory cells. The construction of this term will determine whether this geometric alignment alone is sufficient, or if a more functional or comprehensive similarity between the data and configuration arrays is required.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent describes the invention as "aligning the wordlines in the configuration array substantially parallel with the wordlines in the data array and aligning the bitlines in the configuration array substantially parallel with the bitlines in the data array" '329 Patent, col. 4:13-18 This language may support an interpretation focused on the geometric alignment of the primary conductive lines.
  • Evidence for a Narrower Interpretation: The summary of the invention and detailed description list numerous other "substantially similar" layouts beyond just wordline/bitline direction, including wordline drivers, bitline drivers, sense amplifiers, and voltage regulators '329 Patent, col. 2:22-40 This may support an argument that "same orientation" implies a holistic similarity in the layout of the array and its peripheral circuits, not just the core cell grid.

For the '853 Patent

• The Term: "the sensing is adjusted based on a position of the one group"
• Context and Importance: This phrase defines the core functional step of the claimed method. The infringement allegation relies on inferring this adjustment from YMTC's purported method of setting pass voltages. The definition of "sensing is adjusted" will be critical to determining if the accused activity meets this limitation. Practitioners may focus on this term because the complaint's evidence for this step is indirect, citing a different YMTC patent.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification provides multiple examples of what can be adjusted, stating, "The adjusting can include adjusting a sensing parameter such as body bias, source voltage, sensing time or sensing pre-charge level, based on the position" '853 Patent, abstract This may support a broad reading that covers any modification to the sensing environment or timing that varies by group.
  • Evidence for a Narrower Interpretation: A defendant may argue that the term implies an active, dynamic adjustment during the sensing operation itself, as opposed to using a static, pre-determined set of operating voltages (like pass voltages) that were established during manufacturing or programming. The patent's focus is on compensating for Vth shifts during a "read or verify process" '853 Patent, col. 3:7-10, which may suggest the adjustment must be part of that specific operation.

VI. Other Allegations

Indirect Infringement

• The complaint alleges inducement of infringement for all asserted patents. The allegations state that YMTC knowingly and intentionally encourages infringement by its subsidiaries (such as YMTI), distributors, and customers in the United States Compl. ¶37 Compl. ¶57 Compl. ¶76 Compl. ¶96 Compl. ¶118 The alleged acts of inducement include creating and disseminating datasheets, technical documentation, and advertisements, as well as providing technical support through U.S.-based personnel, all of which allegedly instruct and encourage others to make, use, or sell the infringing products in the U.S. Compl. ¶38 Compl. ¶58 Compl. ¶77 Compl. ¶97 Compl. ¶119

Willful Infringement

• Willfulness is alleged for all asserted patents. The basis for willfulness is alleged knowledge of the patents and infringement starting from the date the original complaint was served (November 26, 2025), and further detailed knowledge from the date infringement contentions were served (March 12, 2026) Compl. ¶41 Compl. ¶61 Compl. ¶80 Compl. ¶100 Compl. ¶122 The complaint alleges that despite this knowledge, YMTC has continued its infringing conduct, warranting enhanced damages for post-filing infringement.

VII. Analyst's Conclusion: Key Questions for the Case

1. A core issue will be one of evidentiary sufficiency: For the method patents ('853, '838, '314, '974), the complaint's infringement theories are largely built on inferences drawn from reverse-engineering the final product and citing YMTC's own patents and technical papers. A key question for the court will be whether this indirect evidence can definitively prove that YMTC's devices and manufacturing processes actually perform the specific steps required by the claims, or if there is a gap between the alleged structure and the claimed function or method.

2. A second key issue will be one of claim scope and technical overlap: The infringement theory for the '853 patent, which claims adjusting a "sensing" operation, relies on evidence of YMTC adjusting a "pass voltage" to mitigate "pass disturb." This raises a critical question of technical and legal scope: can a process for mitigating a programming-related disturbance be construed as the claimed method of adjusting a sensing operation to compensate for a different physical effect (the back-pattern effect)?

3. Finally, the case may turn on a question of structural interpretation: For the '329 patent, can the apparatus claim limitation of a "same orientation" between a data array and a configuration array be satisfied by the observation of a uniform grid of memory cells across a die, or does the patent's specification demand a more comprehensive and functional similarity in the layout of the distinct support circuits for each array?