WeCrevention Inc v. Dell Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: WeCrevention, Inc. (Texas)
  • Defendant: Dell Inc. and Dell Technologies, Inc. (Delaware)
  • Plaintiff's Counsel: Fabricant LLP
• Case Identification: 2:25-cv-01040, E.D. Tex., 10/10/2025
• Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas based on Dell's purported regular and established places of business within the district. These include a secured area within a partner's facility, the homes of remote employees, the physical locations of Dell-affiliated partners, Dell's provision of managed services at a customer's office, and the presence of authorized retail sellers.
• Core Dispute: Plaintiff alleges that Defendant's laptops and other computer products incorporating LPDDR5 and LPDDR5x DRAM infringe five patents related to reconfigurable memory module architecture and low-power dynamic random access memory (DRAM) operation.
• Technical Context: The case concerns the architecture and power management of memory subsystems, a critical technology for balancing performance and battery life in modern portable electronics like laptops and tablets.
• Key Procedural History: The complaint does not reference any prior litigation involving the patents-in-suit, any prior or pending administrative proceedings such as inter partes reviews, or any known licensing history.

Case Timeline

Date	Event
2011-10-11	U.S. Patent No. 9,164,942 Priority Date
2011-10-11	U.S. Patent No. 9,201,834 Priority Date
2012-07-17	U.S. Patent No. 10,998,017 Priority Date
2012-07-17	U.S. Patent No. 11,894,098 Priority Date
2012-07-17	U.S. Patent No. 12,154,652 Priority Date
2015-10-20	U.S. Patent No. 9,164,942 Issued
2015-12-01	U.S. Patent No. 9,201,834 Issued
2019-09-01	Alleged first sale of Accused Products
2021-05-04	U.S. Patent No. 10,998,017 Issued
2024-02-06	U.S. Patent No. 11,894,098 Issued
2024-11-26	U.S. Patent No. 12,154,652 Issued
2025-10-10	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,201,834 - "Reconfigurable high speed memory chip module and electronic device with a reconfigurable high speed memory chip module"

The Invention Explained

• Problem Addressed: The patent addresses the technical challenges arising from integrating advanced memory chips with logic units (like processors), which often use different semiconductor manufacturing processes Compl. ¶34 '942 Patent, col. 1:36-44 This mismatch can lead to poor heat dissipation, high power consumption, and noise interference, as standard memory interfaces are not optimized for specific logic units.
• The Patented Solution: The invention describes a memory module architecture with a reconfigurable interface between the memory chips and an application-specific integrated circuit (ASIC) processor. This is achieved through two distinct transmission buses: a first bus between a logic unit and the memory chips, and a second bus between that logic unit and the ASIC processor, where both buses have programmable characteristics like data rate and signal swing '834 Patent, abstract '834 Patent, col. 2:4-20 This allows the interface to be dynamically configured to optimize performance and power for a specific processor.
• Technical Importance: This reconfigurable bus architecture allows a standardized memory module to be flexibly adapted for various processors and applications, potentially reducing design complexity and improving power efficiency in electronic devices.

Key Claims at a Glance

• The complaint asserts independent claim 21 Compl. ¶34
• The essential elements of claim 21 include:
  • An electronics system device with a reconfigurable high speed memory chip module.
  • An application-specific integrated circuit (ASIC) processor.
  • A memory cell array group comprising multiple memory cell array ICs.
  • A first transmission bus coupled to the memory group, having a first programmable data rate and signal swing corresponding to firmware or software in the ASIC.
  • A logic unit coupled to the first bus for accessing the memory group.
  • A second transmission bus coupled between the logic unit and the ASIC processor, having a second programmable data rate and signal swing associated with the firmware or software in the ASIC.
• The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 10,998,017 - "Dynamic random access memory applied to an embedded display port"

The Invention Explained

• Problem Addressed: The patent identifies a power consumption issue in portable devices that use an embedded Display Port (eDP) with a panel self-refresh (PSR) feature '017 Patent, col. 1:47-52 While PSR is designed to save power by allowing the main graphics processor to turn off, it requires a dedicated frame buffer (DRAM) in the display's timing controller, and the operation of this standard DRAM increases the timing controller's power consumption, partially offsetting the intended savings '017 Patent, col. 1:52-58
• The Patented Solution: The invention proposes a DRAM architecture where the core memory cells and the peripheral circuits operate at voltages lower than 1.1V, which is below the levels specified by conventional JEDEC standards for DRAM of that era '017 Patent, abstract This lower operating voltage reduces the DRAM's overall power consumption, making it more suitable as a frame buffer for power-sensitive eDP applications and thereby extending the battery life of portable devices '017 Patent, col. 2:20-35
• Technical Importance: The technology enables the creation of more power-efficient display subsystems in battery-powered devices by reducing the parasitic power draw of necessary components like frame buffers.

Key Claims at a Glance

• The complaint asserts independent claim 1 Compl. ¶50
• The essential elements of claim 1 include:
  • A dynamic random access memory (DRAM).
  • A DRAM core cell supplied with a first voltage lower than 1.1V.
  • A peripheral circuit electrically connected to the core cell, supplied with a second voltage lower than 1.1V.
  • The core cell and peripheral circuit are formed on a single chip, with the peripheral circuit being external to the core cell.
  • The first and second voltages are capable of making the DRAM be applied to an embedded display port (eDP).
• The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 11,894,098 - "Dynamic random access memory applied to an embedded display port"

• Technology Synopsis: This patent is related to the '017 Patent and similarly describes a low-power DRAM. The key distinction in the asserted claim is the explicit requirement that the first voltage supplied to the DRAM core cell is different from the second voltage supplied to the peripheral circuit, with both voltages remaining below 1.1V '098 Patent, claim 1
• Asserted Claims: Independent claim 1 Compl. ¶64
• Accused Features: The complaint alleges that the Accused Products' LPDDR5 DRAM modules, when operating in Dynamic Voltage and Frequency Scaling (DVFS) mode, use different voltage rails (e.g., VDD2H and VDD2L) for core and peripheral circuits, infringing this patent Compl. ¶¶66-69

U.S. Patent No. 12,154,652 - "Dynamic random access memory applied to an embedded display port"

• Technology Synopsis: Also related to the '017 Patent family, this patent's asserted claim focuses on the voltage relationship between the DRAM core cell and an "input/output circuit." It requires the core cell to operate at a first voltage and the I/O circuit to operate at a third voltage, with both being below 1.1V and the first voltage being different from the third '652 Patent, claim 1
• Asserted Claims: Independent claim 1 Compl. ¶77
• Accused Features: The complaint alleges that the LPDDR5 DRAM in the Accused Products uses distinct power supply rails for the DRAM core cells (e.g., VDD2H/VDD2L) and the I/O circuit (VDDQ), where the voltages are different and below the claimed threshold Compl. ¶¶79-84

U.S. Patent No. 9,164,942 - "High speed memory chip module and electronics system device with a high speed memory chip module"

• Technology Synopsis: Related to the '834 Patent, this patent describes a memory architecture where a logic unit interfaces between multiple memory ICs and an ASIC processor. The asserted claim requires that the logic unit communicates with the memory ICs over a first bus that is wider than the individual I/O data buses of the memory ICs, and that it converts this data for transmission to the ASIC over a second bus, with the bit widths of the data on the first and second buses being different '942 Patent, claim 19
• Asserted Claims: Independent claim 19 Compl. ¶92
• Accused Features: The complaint alleges that the Integrated Memory Controller (IMC) in Intel's Alder Lake processor acts as the logic unit, accessing the LPDDR5 DRAM module over a wide bus (e.g., x128 dual channel) and converting the data for use by the processor cores over a different internal bus structure, thereby infringing Compl. ¶¶97-101

III. The Accused Instrumentality

Product Identification

The complaint identifies the "Accused Products" as Dell products that include LPDDR5 DRAM and LPDDR5x DRAM sold since September 2019 Compl. ¶28 Specific product lines named include XPS, Dell Plus, Latitude, and Precision laptops Compl. ¶28 The Dell XPS 13 Plus 9320 is identified as a representative example for the infringement allegations Compl. ¶35

Functionality and Market Context

The relevant functionality centers on the interaction between the Intel Core i7 "Alder Lake" processor, which serves as the alleged ASIC, and the 16 GB LPDDR5 DRAM module Compl. ¶¶35-37 The complaint highlights the processor's Integrated Memory Controller (IMC) as the alleged "logic unit" that manages communication with the DRAM Compl. ¶38 Compl. ¶41 Key accused technical operations include the system's ability to perform Dynamic Voltage and Frequency Scaling (DVFS), which adjusts operating voltages and frequencies of the memory bus to manage power consumption Compl. ¶39 The complaint also points to the processor's internal "ring interconnect" as a relevant bus for data transfer between the IMC and the processor cores Compl. ¶42

IV. Analysis of Infringement Allegations

'9,201,834 Infringement Allegations

Claim Element (from Independent Claim 21)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
an electronics system device with a reconfigurable high speed memory chip module	The Dell XPS 13 Plus 9320 laptop, which includes a 16 GB LPDDR5 DRAM module.	¶35	col. 2:4-6
an application-specific integrated circuit (ASIC) processor	The Intel Core i7 "Alder Lake" processor.	¶36	col. 2:7
a type of memory cell array group, wherein the type of memory cell array group comprises multiple memory cell array ICs	The 16 GB LPDDR5 DRAM module, which is comprised of multiple memory ICs.	¶37	col. 2:9-11
a first transmission bus coupled to the type of memory cell array group having a first programmable transmitting or receiving data rate, a first programmable transmitting or receiving signal swing corresponding to firmware or software comprised in the ASIC processor	The memory bus connecting the Alder Lake processor's Integrated Memory Controller (IMC) to the LPDDR5 DRAM module, which supports dynamic frequency and voltage scaling controlled by processor firmware/software. A diagram shows this connection between the "Memory Subsystem" and "LPDDR or DDR DRAM" Compl. p. 14	¶38	col. 2:12-16
a logic unit coupled to the first transmission bus for accessing the type of memory cell array group through the first transmission bus	The Integrated Memory Controller (IMC) within the Alder Lake processor.	¶41	col. 2:17-19
and a second transmission bus coupled between the logic unit and the ASIC processor having a second programmable transmitting or receiving data rate, a second programmable transmitting or receiving signal swing associated to the firmware or the software comprised in the ASIC processor	The "ring interconnect" within the Alder Lake processor that connects the IMC to the processor cores (P-cores and E-cores) and supports dynamic frequency and voltage changes based on processor state. A diagram in the complaint illustrates this internal ring interconnect Compl. p. 19	¶42	col. 2:20-25

'10,998,017 Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a DRAM core cell, wherein the DRAM core cell is supplied with a first voltage within a first voltage range to make the DRAM core cell operate at the first voltage...wherein the first voltage is lower than 1.1V	The LPDDR5 DRAM module contains core cells that, in DVFSC mode, can be powered by either the VDD2H or VDD2L voltage rail, which have typical operating ranges below 1.1V (e.g., 1.05V and 0.9V respectively). A table of recommended DC operating conditions is provided as evidence (Compl. p. 24).	¶52; ¶53	col. 6:1-4
and a peripheral circuit electrically connected to the DRAM core cell, wherein the peripheral circuit is supplied with a second voltage within a second voltage range to make the peripheral circuit operate at the second voltage, wherein the second voltage is lower than 1.1V	The LPDDR5 DRAM module includes buffers and data path circuits (alleged to be the peripheral circuit) that are also powered by the VDD2H or VDD2L rails, which are below 1.1V. A diagram illustrates "Peri" (peripheral) circuits powered by these rails (Compl. p. 25).	¶54	col. 6:5-10
and wherein the DRAM core cell and the peripheral circuit are formed on a single chip, and the peripheral circuit is external to the DRAM core cell	The complaint alleges on information and belief that the LPDDR5 DRAM module's core cells and peripheral circuits are formed on a single chip module and are externally located relative to each other.	¶55	col. 6:11-14
wherein the first voltage and the second voltage are capable of making the DRAM be applied to an embedded display port (eDP)	The complaint alleges on information and belief that the accused Dell devices use an eDP protocol for their embedded displays and that the LPDDR5 DRAM module may be applied to an eDP.	¶56	col. 6:15-17

Identified Points of Contention

• Scope Questions: The infringement theory for the '834 Patent identifies the processor's internal memory controller (IMC) as the "logic unit" and the on-chip ring interconnect as the "second transmission bus." This raises the question of whether an internal component of a processor can be considered a separate "logic unit" and whether an on-chip interconnect qualifies as a "bus coupled between the logic unit and the ASIC processor," when all three may be considered parts of the same integrated circuit.
• Technical Questions: For the '017 Patent, the complaint alleges the DRAM's low-voltage operation makes it "capable of" being applied to an eDP. A key question will be what evidence demonstrates this specific capability, beyond the general power-saving benefits of low-voltage operation. The analysis may depend on whether "capable of" requires specific adaptation for eDP use or if general suitability is sufficient.

V. Key Claim Terms for Construction

The Term: "logic unit" (from '834 Patent, claim 21)

• Context and Importance: This term is central to the infringement analysis of the '834 Patent. The complaint maps this term to the Integrated Memory Controller (IMC) within the Alder Lake processor Compl. ¶41 The case may turn on whether the IMC is considered a distinct "logic unit" or an inseparable part of the "ASIC processor" itself.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent specification may describe the logic unit in functional terms as a controller that manages access to the memory group, which could support reading the term on a functional block like an IMC regardless of its physical integration.
  • Evidence for a Narrower Interpretation: The patent's figures, such as Figure 1, depict the "logic unit" (106) and the "ASIC processor" (112) as structurally separate blocks connected by a bus (110) '834 Patent, FIG. 1 This depiction may support an argument that the claim requires two distinct, separately identifiable components rather than functional zones within a single monolithic processor.

The Term: "peripheral circuit" (from '017 Patent, claim 1)

• Context and Importance: The complaint identifies "buffers and other data path circuits" within the LPDDR5 DRAM module as the "peripheral circuit" Compl. ¶54 The definition of this term is critical because the claim requires this specific circuit to be supplied by a voltage lower than 1.1V.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification may use the term broadly to refer to any circuitry on the DRAM chip that is not part of the memory core array itself, which would likely encompass the accused buffers and data paths.
  • Evidence for a Narrower Interpretation: The patent's detailed description or figures might provide specific examples of what constitutes a "peripheral circuit unit" (e.g., item 104 in FIG. 1) '017 Patent, FIG. 1 A defendant may argue that the term is limited to the specific types of circuits disclosed in the patent's embodiments, raising a factual question as to whether the accused LPDDR5 circuits fall within that narrower definition.

VI. Other Allegations

Indirect Infringement

The complaint alleges Dell induces infringement by providing the Accused Products along with "instructions, documentation, ... technical support, marketing, product manuals, advertisements, and online documentation" that allegedly encourage infringing use by customers Compl. ¶44 Compl. ¶58 Compl. ¶71 Compl. ¶86 Compl. ¶103 It also alleges contributory infringement, stating the accused components are material to the inventions, are not staple articles of commerce, and are known by Dell to be especially adapted for an infringing use Compl. ¶45 Compl. ¶59 Compl. ¶72 Compl. ¶87 Compl. ¶104

Willful Infringement

The complaint alleges willful infringement based on two theories. First, it alleges pre-suit knowledge or willful blindness, asserting that Dell as a major technology company regularly monitors memory technology advances and adopted a policy of not reviewing patents to remain willfully blind to its infringement Compl. ¶29 Second, it alleges post-suit knowledge, stating that the filing of the complaint provides Dell with actual knowledge, and any continued infringement is therefore willful Compl. ¶30

VII. Analyst's Conclusion: Key Questions for the Case

• A core issue will be one of architectural interpretation: can functional blocks within a single, monolithic processor-specifically, an integrated memory controller and an on-chip ring interconnect-satisfy the claim requirements for a distinct "logic unit" and a "second transmission bus" coupled to an "ASIC processor," or do the claims of the '834 and '942 patents require greater structural separation between components?
• A central dispute for the '017, '098, and '652 patents will be one of technical causality: does the evidence show that the low-voltage and multi-rail power schemes of LPDDR5 DRAM are merely general-purpose power-saving features, or do they provide a specific technical capability that enables the DRAM to be "applied to an embedded display port," as the claims require?
• The case will likely involve a significant battle over claim construction: the definitions of foundational terms like "logic unit," "transmission bus," and "peripheral circuit" will be critical, as the infringement theories rely on mapping these patent-specific terms onto the complex, integrated components of modern processors and memory modules.