Yangtze Memory Tech Co Ltd v. Micron Technology Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Yangtze Memory Technologies Company, Ltd. (China)
  • Defendant: Micron Technology, Inc. (Delaware); Micron Semiconductor Products, Inc. (Idaho); Micron Technology Texas, LLC (Idaho); and Avnet, Inc. (New York)
  • Plaintiff's Counsel: Miller Fair Henry PLLC
• Case Identification: 2:25-cv-01010, E.D. Tex., 10/06/2025
• Venue Allegations: Venue is alleged to be proper based on Defendants' regular and established places of business within the Eastern District of Texas, including offices in Allen, Richardson, and Plano, and because they have allegedly committed acts of patent infringement within the district.
• Core Dispute: Plaintiff alleges that Defendant's 3D NAND flash memory and DRAM memory products, and devices incorporating them, infringe eight U.S. patents related to semiconductor device architecture, fabrication methods, and operation.
• Technical Context: The lawsuit concerns 3D NAND and DRAM technologies, which are foundational components for high-density data storage in a vast range of modern electronics, from mobile devices and personal computers to large-scale data centers.
• Key Procedural History: The complaint alleges a competitive dynamic where Micron, a primary competitor, has lagged YMTC in innovation and is now using YMTC's patented technologies. It also asserts that many YMTC-owned patents are cited on the face of Micron's own patents, which it frames as evidence of Micron's knowledge of YMTC's patent portfolio.

Case Timeline

Date	Event
2019-05-05	Priority Date for U.S. Patent No. 10,707,851
2019-12-24	Priority Date for U.S. Patent No. 12,068,250
2020-02-01	Micron announces mass production of LPDDR5 products (approximate date)
2020-03-23	Priority Date for U.S. Patent No. 12,232,313
2020-04-27	Priority Date for U.S. Patent No. 11,233,066
2020-05-06	Priority Date for U.S. Patent No. 12,254,925
2020-07-07	U.S. Patent No. 10,707,851 Issues
2020-10-20	Micron announces mass production readiness for uMCP5 with LPDDR5
2021-05-17	Priority Date for U.S. Patent No. 12,266,403
2021-05-28	Priority Date for U.S. Patent No. 12,075,621
2021-12-22	Priority Date for U.S. Patent No. 12,094,767
2022-01-25	U.S. Patent No. 11,233,066 Issues
2024-07-31	Micron's ISO 9001 Certificate becomes valid
2024-08-20	U.S. Patent No. 12,068,250 Issues
2024-08-27	U.S. Patent No. 12,075,621 Issues
2024-09-17	U.S. Patent No. 12,094,767 Issues
2025-02-18	U.S. Patent No. 12,232,313 Issues
2025-03-18	U.S. Patent No. 12,254,925 Issues
2025-04-01	U.S. Patent No. 12,266,403 Issues
2025-10-06	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 11,233,066 - "Three-Dimensional Memory Device and Method for Forming the Same"

• Patent Identification: U.S. Patent No. US11233066B2, "Three-Dimensional Memory Device and Method for Forming the Same," issued January 25, 2022.

The Invention Explained

• Problem Addressed: The patent describes challenges in advanced 3D NAND devices, particularly the complexity of performing erase operations using a P-well, which requires an inversion channel and complicates control of the source select gate '066 Patent, col. 4:13-24 Another problem is avoiding "SONO punch," where etching channel holes can damage underlying structures '066 Patent, col. 4:4-9
• The Patented Solution: The invention proposes a 3D memory device built on an N-type doped semiconductor layer over an N-type doped region of a substrate '066 Patent, col. 4:25-30 This structure enables an erase operation using Gate-Induced-Drain-Leakage (GIDL), which eliminates the need for a P-well and its associated control complexities '066 Patent, col. 4:35-40 A key structural feature is a source contact structure with a lower portion (in the N-type doped region) that is laterally wider than its upper portion (in the memory stack), as depicted in FIG. 1 '066 Patent, abstract '066 Patent, col. 7:55-8:4
• Technical Importance: This approach simplifies the architecture and operation of high-density 3D NAND memory, potentially improving manufacturing yield and device reliability by removing the complex P-well structure.

Key Claims at a Glance

• The complaint asserts at least independent Claim 1 Compl. ¶94
• Claim 1 of the '066 Patent requires:
  • A three-dimensional (3D) memory device, comprising:
  • an N-type doped region of a substrate;
  • an N-type doped semiconductor layer on the N-type doped region;
  • a memory stack comprising interleaved conductive and dielectric layers on the N-type doped semiconductor layer;
  • a channel structure extending vertically through the stack and semiconductor layer into the doped region;
  • a source contact structure extending vertically through the stack and semiconductor layer into the doped region;
  • wherein a first lateral dimension of a first portion of the source contact structure surrounded by the N-type doped region is greater than a second lateral dimension of a second portion surrounded by the memory stack; and
  • a third lateral dimension of a third portion of the source contact structure surrounded by the N-type doped semiconductor layer is greater than the second lateral dimension of the second portion.
• The complaint reserves the right to assert additional claims Compl. ¶100

U.S. Patent No. 12,068,250 - "3D NAND Memory Device and Method of Forming the Same"

• Patent Identification: U.S. Patent No. US12068250B2, "3D NAND Memory Device and Method of Forming the Same," issued August 20, 2024.

The Invention Explained

• Problem Addressed: As 3D NAND technology scales to higher layer counts (e.g., from 64 to 128 layers), forming the staircase structure that provides access to word lines becomes more time-consuming. Additionally, the increased length of word lines at the bottom of the stack can lead to high resistance-capacitance (RC) delays, slowing down device operation '250 Patent, col. 6:5-15
• The Patented Solution: The patent discloses a device architecture with array regions positioned at opposing sides of the memory stack '250 Patent, col. 1:30-34 Between these arrays, a connection region contains a first and a second staircase. The "first staircase" is notable for having two groups of stairs with opposite step-down directions that converge at a shared stair '250 Patent, col. 1:45-48 This structure is intended to solve RC delay and fabrication complexity issues '250 Patent, col. 18:15-22
• Technical Importance: This novel staircase configuration aims to optimize the layout and electrical connections in very high-density 3D NAND, addressing key performance bottlenecks like RC delay and manufacturing challenges that arise with increasing vertical stacking.

Key Claims at a Glance

• The complaint asserts at least independent Claim 1 Compl. ¶121
• Claim 1 of the '250 Patent requires:
  • A semiconductor device, comprising:
  • a stack of word line layers and insulating layers stacked alternatingly;
  • channel structures formed in a first and second array region of the stack, positioned at opposing sides;
  • a first staircase and a second staircase formed between the first and second array regions;
  • a portion of the stack positioned between the staircases and between the array regions;
  • wherein the first staircase has first stairs with a first step-down direction and second stairs with a second, opposite step-down direction; and
  • each of the first and second stairs corresponds to a different word line layer.
• The complaint reserves the right to assert additional claims Compl. ¶127

U.S. Patent No. 12,094,767 - "Barrier Layers for Word Line Contacts in a Three-Dimensional NAND Memory and Fabrication Methods Thereof"

• Patent Identification: U.S. Patent No. US12094767B2, "Barrier Layers for Word Line Contacts in a Three-Dimensional NAND Memory and Fabrication Methods Thereof," issued September 17, 2024.
• Technology Synopsis: The patent addresses problems in fabricating contacts for word lines in high-density 3D NAND Compl. ¶58 To prevent over-etching, an etch-stop layer is used, but this layer can be lost during processing or cause other defects '767 Patent, col. 1:42-50 The invention discloses a method using two different barrier layers on the staircase structure to provide more robust protection during the contact formation process '767 Patent, col. 2:1-3
• Asserted Claims: At least Claim 1 Compl. ¶147
• Accused Features: The complaint alleges that Micron's 232L and 276L Accused Products, including its 2550 and 2650 SSDs, embody the claimed memory device with its specific film stack, staircase structure, dividing wall, and barrier layer configuration Compl. ¶¶149-152

U.S. Patent No. 12,075,621 - "Three-Dimensional Memory Device and Method for Forming the Same"

• Patent Identification: U.S. Patent No. US12075621B2, "Three-Dimensional Memory Device and Method for Forming the Same," issued August 27, 2024.
• Technology Synopsis: This patent relates to 3D semiconductor devices formed by stacking separate wafers or dies vertically to achieve higher performance, reduced power, and a smaller footprint '621 Patent, col. 1:32-38 The invention discloses a specific structure where the drain select gate line and the plurality of word lines are made of the same material, and the drain select gate line is in direct contact with the semiconductor channel, while the word lines are in direct contact with the memory film '621 Patent, col. 1:55-59
• Asserted Claims: At least Claim 1 Compl. ¶172
• Accused Features: The complaint accuses Micron's 276L products (e.g., 2650 SSD with B68S die) of infringing Compl. ¶¶171 Compl. ¶174 It alleges these products have the claimed doped semiconductor layer, stack structure, and channel structure where the drain select gate line and word lines are made of the same material and have the specified contacts Compl. ¶¶175-176

U.S. Patent No. 12,232,313 - "Staircase Structure in Three-Dimensional Memory Device and Method for Forming the Same"

• Patent Identification: U.S. Patent No. US12232313B2, "Staircase Structure in Three-Dimensional Memory Device and Method for Forming the Same," issued February 18, 2025.
• Technology Synopsis: The patent addresses density limitations in planar memory by introducing a novel staircase structure for 3D NAND devices '313 Patent, col. 1:30-43 The invention discloses a staircase structure located between two memory arrays, which is itself divided into zones connected by a bridge structure. This architecture is intended to enable a bilateral wordline driving scheme to reduce RC delay and fabrication complexity '313 Patent, abstract
• Asserted Claims: At least Claim 1 Compl. ¶195
• Accused Features: The complaint accuses Micron's 232L and 276L products (e.g., 2550 and 2650 SSDs) of having the claimed memory array structures with the intermediate staircase structure, bridge structures, and specific sub-staircase configurations Compl. ¶¶197-200

U.S. Patent No. 12,266,403 - "Three-Dimensional NAND Memory and Fabrication Method Thereof"

• Patent Identification: U.S. Patent No. US12266403B2, "Three-Dimensional NAND Memory and Fabrication Method Thereof," issued April 1, 2025.
• Technology Synopsis: This patent addresses the challenge of shrinking process windows as 3D memory device feature sizes are scaled down to increase density '403 Patent, col. 1:27-41 It discloses a manufacturing method using an etch-stop layer positioned on the outermost side of a top select gate (TSG) film stack, which functions as an etch stop for forming both the bit line (BL) contact opening and the gate line slit (GLS) trench '403 Patent, abstract
• Asserted Claims: At least Claim 1 (a method claim) Compl. ¶221
• Accused Features: The complaint alleges that the process used to manufacture Micron's 276L Accused Products (e.g., 2650 SSD) infringes the claimed method Compl. ¶¶220 Compl. ¶223 It alleges the manufacturing process involves forming the claimed dielectric stacks, etch-stop layer, and GLS trench and opening Compl. ¶¶224-228

U.S. Patent No. 12,254,925 - "Control Method and Controller of 3D NAND Flash"

• Patent Identification: U.S. Patent No. US12254925B2, "Control Method and Controller of 3D NAND Flash," issued March 18, 2025.
• Technology Synopsis: The patent seeks to enhance programming performance for 3D NAND flash, particularly for multi-level cell (MLC/TLC/QLC) devices where programming time is critical '925 Patent, col. 1:18-21 '925 Patent, col. 1:48-52 The invention is a control method that adjusts the pulse widths of the programming voltage pulses during a programming stage, in contrast to using uniform pulse widths '925 Patent, col. 1:53-64
• Asserted Claims: At least Claim 1 (a method claim) Compl. ¶246
• Accused Features: The complaint alleges that Micron's 176L Accused Products (e.g., 2400 and 2450 SSDs) practice the claimed method by using a programming operation with varied pulse widths, such as a wider first middle pulse and an even wider last pulse Compl. ¶¶248 Compl. ¶251

U.S. Patent No. 10,707,851 - "Double Data Rate Circuit and Data Generation Method Implementing Precise Duty Cycle Control"

• Patent Identification: U.S. Patent No. US10707851B1, "Double Data Rate Circuit and Data Generation Method Implementing Precise Duty Cycle Control," issued July 7, 2020.
• Technology Synopsis: The patent relates to high-speed Double Data Rate (DDR) circuits, where data is transferred on both rising and falling edges of a clock signal '851 Patent, col. 1:22-23 The problem is that imbalances in the circuit can lead to a poor duty cycle (not 50%), which degrades timing performance. The invention is a DDR circuit that uses a specific combination of NAND gates with matched pull-up and pull-down paths to generate a precise, 50%-duty-cycle clock, thereby reducing data skew and errors '851 Patent, abstract '851 Patent, col. 4:10-24
• Asserted Claims: At least Claim 1 Compl. ¶270
• Accused Features: The complaint accuses Micron's LPDDR5 and LPDDR5X DRAM products of infringement Compl. ¶268 It alleges these products contain a double data rate circuit with the claimed clock generator, clock divider, and multiplexer composed of 3-input and 4-input NAND gates with matched paths Compl. ¶¶272 Compl. ¶¶274-281

III. The Accused Instrumentality

Product Identification

• The complaint identifies several categories of accused products: 176-layer NAND devices ("176L Accused Products"), 232-layer NAND devices ("232L Accused Products"), 276-layer NAND devices ("276L Accused Products"), Low-Power DDR5 DRAM devices ("LPDDR5 Accused Products"), and Low-Power DDR5X DRAM devices ("LPDDR5X Accused Products") Compl. ¶84 Specific examples cited include Micron SSDs such as the 2400, 2450, 2550, and 2650 series (Compl. ¶91; Compl. ¶119; Compl. ¶145; Compl. ¶171; Compl. ¶245).

Functionality and Market Context

• The Accused Products are semiconductor memory components that serve as the core data storage element in a wide array of electronic devices, from mobile phones and PCs to enterprise data centers Compl. ¶4 Compl. ¶83 The complaint highlights specific technical features marketed by Micron, such as the "industry-leading 232-layer NAND" with "100% higher write bandwidth" in the Micron 2550 SSD and the "ninth-generation 3D NAND" in the 2650 SSD Compl. ¶97 Compl. p. 31 An infographic for Micron's G9 NAND, incorporated into the 276L products, emphasizes its high "Bit density per square millimeter" Compl. ¶¶52 Compl. p. 32 The complaint positions these products as central to Micron's business, alleging they contributed to over $5 billion in net income in the first three quarters of fiscal year 2025 Compl. ¶87

IV. Analysis of Infringement Allegations

U.S. Patent No. 11,233,066 Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
an N-type doped region of a substrate;	The 232L and 276L Accused Products are alleged to include an N-type doped region of a substrate.	¶98	col. 4:25-30
an N-type doped semiconductor layer on the N-type doped region;	The Accused Products allegedly include an N-type doped semiconductor layer on the N-type doped region.	¶98	col. 4:25-30
a memory stack comprising interleaved conductive layers and dielectric layers on the N-type doped semiconductor layer;	The Accused Products are alleged to contain a memory stack with interleaved conductive and dielectric layers. A cited infographic shows the layered structure of Micron's G8 and G9 NAND.	¶98; ¶52	col. 5:26-37
a channel structure extending vertically through the memory stack and the N-type doped semiconductor layer into the N-type doped region;	The Accused Products allegedly contain a channel structure that extends vertically through the memory stack and into the N-type doped region.	¶99	col. 6:58-7:4
a source contact structure extending vertically through the memory stack and the N-type doped semiconductor layer into the N-type doped region, wherein: a first lateral dimension of a first portion of the source contact structure surrounded by the N-type doped region is greater than a second lateral dimension of a second portion...surrounded by the memory stack; and a third lateral dimension of a third portion...is greater than the second lateral dimension...	The Accused Products allegedly contain a source contact structure with the claimed dimensional characteristics, where portions of the structure are wider in the N-type doped regions than in the memory stack.	¶99	col. 7:55-8:4

• Identified Points of Contention:
  • Structural and Material Questions: A central issue will be substantiating the material composition and doping profiles of the accused devices. The analysis will require evidence confirming the presence of an "N-type doped region" of a substrate and an "N-type doped semiconductor layer" as claimed, rather than alternative architectures (e.g., P-well based).
  • Dimensional Questions: The infringement allegation hinges on specific dimensional relationships of the "source contact structure." A key point of contention will be whether the accused devices' physical structures satisfy the "greater than" limitations for the first and third lateral dimensions compared to the second, which will likely require detailed reverse engineering and metrology evidence.

U.S. Patent No. 12,068,250 Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a stack of word line layers and insulating layers that are stacked alternatingly;	The 232L and 276L Accused Products are alleged to be semiconductor devices that include a stack of alternatingly stacked word line and insulating layers.	¶125	col. 3:30-34
channel structures formed in a first array region and a second array region of the stack, the first array region and the second array region being positioned at opposing sides of the stack...	The Accused Products allegedly include channel structures in first and second array regions positioned at opposing sides of the stack.	¶126	col. 1:30-34
a first staircase is formed between the first array region and the second array region,	The Accused Products allegedly include a first staircase formed between the first and second array regions.	¶126	col. 1:35-42
a second staircase is formed between the first array region and the second array region,	The Accused Products are alleged to include a second staircase formed between the first and second array regions.	¶126	col. 1:35-42
the first staircase has first stairs with a first step-down direction and second stairs with a second step-down direction, the first step-down direction being opposite to the second step-down direction...	The complaint alleges on information and belief that the first staircase in the Accused Products has first stairs with a first step-down direction and second stairs with a second, opposite step-down direction.	¶126	col. 1:45-48

• Identified Points of Contention:
  • Architectural Mapping: The core of the dispute will be whether Micron's staircase architecture, as implemented in its high-layer-count NAND, maps onto the patent's specific configuration. A key question is whether the accused devices' staircase truly has distinct "first stairs" and "second stairs" with "opposite" step-down directions that "converge at a first shared stair" as the claim and specification require '250 Patent, col. 1:45-48
  • Scope Questions: The term "opposing sides of the stack" will likely be scrutinized. The dispute may focus on whether the accused product's architecture, described as having a "six-plane production TLC NAND" Compl. ¶125, fits the claimed arrangement of two array regions on "opposing sides."

V. Key Claim Terms for Construction

Patent: U.S. Patent No. 11,233,066

• The Term: "a first lateral dimension of a first portion of the source contact structure ... is greater than a second lateral dimension of a second portion"
• Context and Importance: This dimensional relationship is a critical limitation differentiating the claimed invention. Infringement requires proving that the accused device's source contact is physically wider in the substrate region than in the memory stack region. Practitioners may focus on this term because it is a precise, measurable structural feature that will be a primary focus of expert analysis and reverse engineering.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent's broad description of the structure as solving the GIDL-assisted body biasing problem could support an interpretation covering any structure that achieves this function and has the general dimensional characteristic, regardless of the exact shape '066 Patent, col. 4:35-40
  • Evidence for a Narrower Interpretation: The specification provides detailed figures (e.g., FIG. 1, FIG. 2H) showing a specific, flared or enlarged shape for the lower portion of the source contact structure '066 Patent, col. 7:55-8:4 A defendant may argue that the term should be limited to the specific shapes and formation methods disclosed in these embodiments.

Patent: U.S. Patent No. 12,068,250

• The Term: "first stairs with a first step-down direction and second stairs with a second step-down direction, the first step-down direction being opposite to the second step-down direction"
• Context and Importance: This term defines the unique geometry of the claimed staircase, which is central to the patent's solution for RC delay and fabrication complexity. The infringement analysis will turn on whether the physical layout of the accused device's staircase meets this "opposite step-down direction" requirement.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: A party might argue that any staircase design that functionally divides the word line connections in a way that reduces RC delay and uses some form of opposing tiered structures falls within the scope, even if not geometrically identical to the figures. The background's focus on solving the RC delay problem could support this '250 Patent, col. 6:5-15
  • Evidence for a Narrower Interpretation: The patent specification provides highly detailed diagrams (e.g., FIG. 4A, FIG. 5) illustrating a very specific V-shaped or converging staircase geometry where stairs descend from two sides toward a central "shared stair" '250 Patent, col. 7:41-52 This provides strong evidence to argue that the claim should be construed narrowly to cover only architectures that replicate this specific opposing and converging arrangement.

VI. Other Allegations

• Indirect Infringement: The complaint alleges Defendants induce infringement by providing customers and distributors (such as co-defendant Avnet) with technical documentation, product briefs, datasheets, and marketing materials that instruct and encourage the use of the Accused Products in an infringing manner Compl. ¶¶102-107 Compl. ¶¶129-134 Specific examples include Micron's website advertising the "first-to-market 232-layer technology" and Avnet promoting the "Key features" and "Applications" of the accused SSDs Compl. ¶131 Compl. ¶132
• Willful Infringement: Willfulness is alleged based on two grounds. First, the complaint claims Defendants have had knowledge of the asserted patents since at least the filing date of the lawsuit (Compl. ¶101; Compl. ¶128). Second, it alleges pre-suit knowledge, asserting that "Many YMTC-owned patents are cited on the face of Micron's own patents," which demonstrates Micron's awareness of YMTC's relevant patent portfolio (Compl. ¶89).

VII. Analyst's Conclusion: Key Questions for the Case

• A central issue for multiple asserted patents will be one of structural mapping: does the physical architecture of Micron's 232L and 276L NAND products, marketed with features like "six-plane NAND," actually embody the specific and unconventional device structures claimed, such as the flared source contact of the '066 patent or the dual, opposing-direction staircases of the '250 patent? This will likely require extensive expert testimony and reverse engineering of the accused chips.
• A second key question will relate to indirect infringement and agency: can YMTC establish that Micron's relationship with its distributor, Avnet, rises to the level of agency, and that their collective marketing, sales, and technical support activities demonstrate a specific intent to induce their customers to infringe the asserted patents? The complaint dedicates significant attention to the "deeply intertwined" relationship between Micron and Avnet Compl. ¶¶26-36
• Finally, the case presents an overarching evidentiary question of timing and knowledge for willfulness: can YMTC prove that Micron had pre-suit knowledge of the specific asserted patents, beyond general awareness of a competitor's portfolio, to support its claim for enhanced damages? The allegation that Micron cited YMTC's patents in its own prosecution history will be a key focal point for this inquiry.