Induction Devices LLC v. Recreational Equipment Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Induction Devices LLC (Texas)
  • Defendant: Penney Opco, LLC d/b/a JCPENNEY (Virginia)
  • Plaintiff's Counsel: Devlin Law Firm LLC
• Case Identification: 2:25-cv-00790, E.D. Tex., 03/12/2026
• Venue Allegations: Venue is based on Defendant maintaining a place of business in Frisco, Texas, and regularly conducting business within the Eastern District of Texas.
• Core Dispute: Plaintiff alleges that Defendant's provision and support of branded contactless consumer credit cards induces infringement of five patents related to fundamental semiconductor circuit design, security, and operation.
• Technical Context: The patents-in-suit cover a range of core semiconductor technologies, including circuit reset mechanisms, low-jitter signal multiplexing, secure memory systems for near-field communication (NFC), asynchronous communication ports, and digital signal processing.
• Key Procedural History: The complaint notes that U.S. Patent No. 7,899,145 was previously litigated in the Western District of Texas in two cases filed in 2021, which were resolved before any substantive matters were addressed.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,449,926 - "Circuit for Asynchronously Resetting Synchronous Circuit"

The Invention Explained

• Problem Addressed: The patent describes the challenge of resetting synchronous circuits, such as those containing a CPU and RAM, under different operating conditions Compl. ¶10 An asynchronous reset during normal operation can cause data loss in memory, while a synchronous reset may be ineffective if the circuit is malfunctioning or the system clock is unstable '926 Patent, col. 1:36-49
• The Patented Solution: The invention is a reset signal generation circuit that intelligently selects the type of reset to perform '926 Patent, abstract An operation detection circuit monitors the CPU to determine if it is functioning "normally" or "abnormally" '926 Patent, col. 4:12-16 Based on this determination, a signal control circuit generates either a synchronous reset signal to preserve data integrity during normal operation, or an asynchronous reset signal to immediately initialize all circuits during an abnormal event Compl. ¶11 '926 Patent, col. 6:58-7:6 The selection can also be based on the power supply voltage level Compl. ¶12
• Technical Importance: This selective reset capability enhances overall circuit reliability by applying the appropriate reset strategy for a given state, thereby preventing data loss in some scenarios while ensuring a complete system recovery in others Compl. ¶11

Key Claims at a Glance

• The complaint asserts at least independent claim 1 Compl. ¶33
• Claim 1 Elements:
  • An operation detection circuit for detecting whether a synchronous circuit is operating normally or abnormally and generating an operation detection signal.
  • A signal control circuit for generating a first reset signal based on a system reset signal, a clock signal, and the operation detection signal.
  • The signal control circuit generates a synchronous first reset signal when the synchronous circuit operates normally.
  • The signal control circuit generates an asynchronous first reset signal when the synchronous circuit operates abnormally.

U.S. Patent No. 7,899,145 - "Circuit, System, and Method for Multiplexing Signals with Reduced Jitter"

The Invention Explained

• Problem Addressed: In high-speed synchronous systems, multiplexers are used to select between different clock signals, but conventional designs can introduce "crosstalk and power supply noise" Compl. ¶16 This noise increases timing variations known as jitter, which can degrade system performance and reliability '145 Patent, col. 2:60-67
• The Patented Solution: The patent discloses a multiplexer circuit designed to reduce jitter Compl. ¶15 The solution involves using a logic block to deactivate one of the input signals, ensuring that only one active signal is supplied to the multiplexer's internal logic gates at any time Compl. ¶17 '145 Patent, col. 3:20-26 This prevents the signals from interfering with each other. The invention further proposes arranging the logic gates in separate power supply domains to provide additional electrical isolation and reduce the injection of power supply noise Compl. ¶17 '145 Patent, col. 3:26-28
• Technical Importance: By minimizing crosstalk and power supply noise at a fundamental circuit level, the invention allows for the creation of cleaner clock signals, which is critical for maintaining timing margins in high-performance electronic systems Compl. ¶16

Key Claims at a Glance

• The complaint asserts at least independent claim 10 Compl. ¶43
• Claim 10 Elements:
  • A system comprising a circuit with two logic gates, a first logic block, and a second logic block, where each is arranged within a separate power supply domain.
  • A first logic gate operatively coupled with a first signal.
  • A second logic gate operatively coupled with a second signal.
  • A second logic block operatively coupled with one of the first and second signals, depending on a control signal's state.
  • A system component coupled to the second logic block.

U.S. Patent No. 8,190,885 - "Non-Volatile Memory Sub-System Integrated with Security for Storing Near Field Transactions"

• Technology Synopsis: The patent describes a memory module designed for securely handling Near Field Communication (NFC) transactions Compl. ¶21 The problem is the vulnerability of NFC systems to unauthorized access and data corruption. The solution integrates an NFC radio frequency component, a dedicated security processor, and non-volatile memory into a single, secure execution environment, which prevents unauthorized access, ensures data integrity, and allows for secure memory partitioning and transaction logging Compl. ¶21 Compl. ¶22
• Asserted Claims: Independent claims 1 and 3 Compl. ¶53
• Accused Features: The integrated circuits within the accused contactless credit cards are alleged to embody the claimed secure memory sub-system for processing NFC payments Compl. ¶53

U.S. Patent No. 8,370,543 - "Busy Detection Logic for Asynchronous Communication Port"

• Technology Synopsis: The patent addresses the technical challenge of synchronizing access to a shared resource (e.g., memory) between two components operating in different, independent clock domains Compl. ¶25 Prior solutions often required restrictive signal pulse widths or complex, power-intensive high-speed clocks Compl. ¶26 The invention provides a system for synchronizing this access without such constraints, which improves the design efficiency and performance of devices with multiple clock domains Compl. ¶27
• Asserted Claims: Independent claim 16 Compl. ¶63
• Accused Features: The chips within the accused credit cards are alleged to use the claimed busy detection logic to manage communication between different internal components Compl. ¶63

U.S. Patent No. 8,543,628 - "Method and System of Digital Signal Processing"

• Technology Synopsis: The patent discloses a dynamically reconfigurable digital signal processing (DSP) system on a chip Compl. ¶30 The system uses a microcontroller to load instruction sets that configure a controller and an address-calculation device. These components, in turn, select specific filter coefficients for a data path device to perform DSP operations on incoming data Compl. ¶30 This architecture is intended to provide dynamic reconfiguration and improve resource efficiency compared to static DSP systems Compl. ¶31
• Asserted Claims: Independent claim 1 Compl. ¶73
• Accused Features: The accused credit cards are alleged to contain the claimed programmable DSP system for processing digital data Compl. ¶73

III. The Accused Instrumentality

Product Identification

• The "Accused Instrumentalities" are identified as "branded contactless consumer credit cards" that Defendant provides and supports Compl. ¶33

Functionality and Market Context

• The complaint alleges that these cards contain semiconductor chips capable of performing contactless transactions Compl. ¶33 The core functionality at issue is the internal operation of these chips, which allegedly practice the technologies claimed in the five patents-in-suit, covering circuit resets, signal multiplexing, secure NFC memory, asynchronous communication, and digital signal processing. The complaint asserts that these cards are marketed and used by Defendant's partners, customers, and end users throughout the United States Compl. ¶35

IV. Analysis of Infringement Allegations

The complaint references external claim-chart exhibits (e.g., Exhibit A-1, B-1) to detail its infringement allegations but does not include them with the pleading Compl. ¶34 Compl. ¶44 The narrative infringement theories are summarized below.

'926 Patent Infringement Theory

• The complaint alleges that Defendant induces infringement by third-party users of the accused contactless credit cards Compl. ¶33 The theory posits that the semiconductor chips within these cards contain a circuit that practices claim 1. This circuit allegedly detects the operational state (normal vs. abnormal) of the chip and selectively generates either a synchronous or an asynchronous reset signal to enhance reliability Compl. ¶10 Compl. ¶11 The complaint does not provide specific technical facts explaining how the accused cards perform this function.

'145 Patent Infringement Theory

• The complaint alleges that by providing and supporting the accused contactless credit cards, Defendant induces infringement of at least claim 10 of the '145 patent Compl. ¶43 The infringement theory is that the chips inside these cards contain a system for multiplexing signals that reduces jitter by utilizing logic gates and blocks arranged in separate power supply domains and deactivating one signal path to eliminate crosstalk Compl. ¶15 Compl. ¶17 The complaint does not offer narrative details on the specific architecture of the accused chips.

No probative visual evidence provided in complaint.

Identified Points of Contention

• Scope Questions: A primary question may be whether the term "operating abnormally" in the '926 patent, which the specification ties to a CPU failing to send a periodic clear signal, can be construed to cover the types of error states that may occur in a standard credit card chip. For the '145 patent, a key dispute may center on whether the accused chips actually contain logic gates and blocks that are "each arranged within a separate power supply domain" as required by claim 10.
• Technical Questions: The complaint's allegations are conclusory. A central evidentiary challenge for the plaintiff will be to demonstrate that the chips in the accused credit cards contain the specific, low-level circuit architectures claimed in the patents. For instance, what evidence shows that an accused card's chip generates both synchronous and asynchronous resets based on a detected operational state ('926 patent)? What evidence shows that its multiplexers operate by deactivating an input signal path to prevent crosstalk, rather than using a conventional design ('145 patent)?

V. Key Claim Terms for Construction

'926 Patent, Claim 1

• The Term: "operating abnormally"
• Context and Importance: The distinction between "normally" and "abnormally" is the trigger for the claimed invention's selective reset function. The definition of this term will be critical to determining whether the error-handling mechanisms in an accused chip fall within the claim's scope.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification describes the abnormal state as one where "a clear signal is not provided from the CPU 11 to the operation detection circuit 21 at the appropriate interval" '926 Patent, col. 4:38-41 This could support a broad interpretation covering any failure of a component to provide an expected periodic status signal.
  • Evidence for a Narrower Interpretation: The patent's embodiment describes a specific mechanism where an "up-counter" exceeds a predetermined value because the CPU fails to clear it '926 Patent, col. 4:18-22 This language may support a narrower construction limited to this specific type of watchdog timer failure.

'145 Patent, Claim 10

• The Term: "each arranged within a separate power supply domain"
• Context and Importance: This limitation is central to the patent's claimed solution for reducing jitter by isolating logic components from power supply noise. Infringement will likely require evidence of this specific physical layout in the accused chips.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent's objective is to "further isolate the logic gate inputs" '145 Patent, col. 3:29-31 An argument could be made that any physical layout achieving sufficient electrical isolation to serve this purpose meets the limitation, even without fully distinct power buses.
  • Evidence for a Narrower Interpretation: The specification explicitly describes arranging logic gates within different "power supply 'islands,' each coupled to a different power bus" '145 Patent, col. 3:32-34 This may support a narrow construction requiring physically distinct, separately powered regions on the semiconductor die.

VI. Other Allegations

Indirect Infringement

• The complaint exclusively pleads induced infringement, alleging Defendant encourages infringement by its customers and partners who use the accused contactless credit cards Compl. ¶33 Compl. ¶43 Compl. ¶53 Compl. ¶63 Compl. ¶73 The basis for intent is Defendant's alleged knowledge of the patents, which the complaint asserts began "at least as early as the filing of this Complaint" Compl. ¶36 The complaint further alleges inducement through actions like "advertising and distributing the Accused Instrumentalities and providing instruction materials" Compl. ¶38

Willful Infringement

• Willfulness is alleged based on Defendant's continued inducement of infringement after gaining knowledge of the patents through the filing and service of the complaint Compl. ¶37 Compl. ¶39

VII. Analyst's Conclusion: Key Questions for the Case

• A key evidentiary question will be one of architectural mapping: can the plaintiff, through reverse engineering or discovery, demonstrate that the general-purpose semiconductor chips in Defendant's branded contactless credit cards contain the specific, low-level circuit architectures required by the patent claims, such as selective-mode reset generators or multiplexers with physically separate power domains? The complaint currently lacks the specific factual allegations to substantiate this link.
• A central legal issue will be one of induced infringement: assuming the underlying credit card chips are found to infringe, the case may turn on whether Plaintiff can prove that Defendant's actions-such as branding and distributing cards for payment transactions-were taken with the specific intent to cause infringement of these particular internal semiconductor circuit designs, of which a retail entity like JCPenney may claim to have no specific knowledge.