Netlist Inc v. Micron Technology Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Netlist, Inc. (Delaware)
  • Defendant: Micron Technology, Inc. (Delaware); Micron Semiconductor Products, Inc. (Idaho); Micron Technology Texas, LLC (Idaho); Avnet, Inc. (New York)
  • Plaintiff's Counsel: McKool Smith, P.C.; Irell & Manella LLP
• Case Identification: 2:25-cv-00749, E.D. Tex., 07/28/2025
• Venue Allegations: Plaintiff alleges venue is proper because Defendants have committed acts of infringement in the district, maintain regular and established places of business in the district, and have placed the accused products into the stream of commerce with the knowledge they would be sold in the district.
• Core Dispute: Plaintiff alleges that Defendant's DDR5 dual in-line memory modules (DIMMs) infringe a patent related to on-module power management architecture.
• Technical Context: The technology involves integrating power management circuits directly onto memory modules, a key feature of the DDR5 memory standard that enables higher data rates and improved power efficiency for high-performance computing.
• Key Procedural History: The complaint was filed one day before the patent-in-suit was scheduled to issue. Plaintiff also references a history of litigation between the parties, including what it characterizes as "retaliatory suits" filed by Micron in Idaho, and seeks a declaratory judgment that its own assertion of the patent is not in bad faith. The complaint also notes prior, multi-hundred-million-dollar jury verdicts Netlist has won against Samsung and Micron involving other memory technology patents.

Case Timeline

Date	Event
2007-06-01	'366 Patent Priority Date
2023-04-21	Prior jury verdict in Netlist v. Samsung (E.D. Tex.)
2023-12-22	Prior related suit filed by Netlist against Micron (E.D. Tex.)
2024-02-07	Amended complaint filed in prior related suit (E.D. Tex.)
2024-05-23	Prior jury verdict in Netlist v. Micron (E.D. Tex.)
2024-11-22	Prior jury verdict in Netlist v. Samsung (E.D. Tex.)
2025-06-24	Prior related suit filed by Micron against Netlist (D. Idaho)
2025-07-28	Complaint Filing Date
2025-07-29	'366 Patent Issue Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 12,373,366 - "Memory with On-Module Power Management"

• Patent Identification: U.S. Patent No. 12,373,366 ("'366 Patent"), "Memory with On-Module Power Management," issued July 29, 2025.

The Invention Explained

• Problem Addressed: The patent's background section describes the performance bottleneck created when a computer's central processing unit (CPU) must manage all data transfers between main storage (like a hard disk) and memory subsystems (like DRAM DIMMs), which can limit overall server performance. '366 Patent, col. 1:12-40
• The Patented Solution: The invention describes a memory module that integrates its own power management capabilities directly onto the printed circuit board (PCB). It receives a main input voltage from the system board and uses multiple on-module converter circuits to generate several different regulated voltages required by various components on the module, such as the memory chips themselves. '366 Patent, abstract '366 Patent, col. 28:25-41 The module also includes a controller that can monitor the input voltage and trigger a write operation to non-volatile memory if the voltage exceeds a threshold. '366 Patent, abstract
• Technical Importance: Moving power management from the motherboard to the memory module itself allows for more precise voltage control, which is necessary to support the higher data rates and improve power efficiency in newer generations of memory like DDR5. Compl. ¶32

Key Claims at a Glance

• The complaint asserts independent claim 1. Compl. ¶¶34-78
• The essential elements of independent claim 1 include:
  • A dual in-line memory module (DIMM) with a PCB having specific sets of edge connections for power, data, and address/control conduits.
  • A key negative limitation that the power delivered from the system board's power rails is the "only power received by the DIMM."
  • A "controller" on the PCB that includes a voltage monitor circuit and nonvolatile memory, where the voltage monitor is configured to trigger a write operation to the nonvolatile memory if the input voltage exceeds a threshold.
  • A set of components on the PCB, including DDR SDRAM devices.
  • First, second, third, and fourth "converter circuits" on the PCB that receive power from an input voltage supply line and deliver four distinct regulated voltage lines to the components.
  • A specific arrangement of the DDR SDRAM devices into a first group of at least five and a second group of at least four, which are configured to operate independently.
• The complaint does not explicitly reserve the right to assert dependent claims.

III. The Accused Instrumentality

Product Identification

The complaint identifies the "Accused DDR5 Products," which include Micron's DDR5 memory modules, such as DDR5 Registered DIMMs (RDIMMs) and other products with similar structures. Compl. ¶29

Functionality and Market Context

The accused products are DDR5 memory modules used in servers for cloud computing, artificial intelligence, and other data-intensive applications. Compl. ¶22 The complaint alleges these modules incorporate the key features of the DDR5 standard, including two independent 40-bit channels (32 data bits plus 8 ECC bits) and an on-module Power Management Integrated Circuit (PMIC). Compl. ¶¶31-32 This on-module PMIC is alleged to provide more precise voltage control and reduce power loss compared to prior DDR4 technology, where power management was handled on the motherboard. Compl. ¶32 The complaint includes a diagram from a Micron technical brief illustrating the layout of a DDR5 module, which shows a centrally located PMIC separating two independent 40-bit subchannels. Compl. ¶49

IV. Analysis of Infringement Allegations

'366 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a printed circuit board (PCB) having edge connections configured to fit into the memory slot connector of the system board, the PCB including: a first set of edge connections configured to be electrically connected to the set of power conduits and operable to deliver to the DIMM power from power rails of the system board via the set of power conduits, wherein the power delivered to the DIMM from the power rails of the system board is the only power received by the DIMM	The accused DDR5 products are DIMMs with a PCB and edge connections ("gold fingers") that fit into a system board's memory slot. The DIMM power supply is delivered from the system to the on-module PMIC, and this is alleged to be the only power received.	¶¶38-41	col. 37:45-51
a controller including a voltage monitor circuit and nonvolatile memory, the controller coupled to the PCB and to an input voltage supply line ... the voltage monitor circuit configured to: (i) monitor an input voltage ... (ii) generate a trigger signal upon detecting a trigger condition; and (iii) transmit the trigger signal ... wherein the controller is configured to perform, in response to the trigger signal, a write operation to write data into the nonvolatile memory, and wherein the trigger condition occurs when the input voltage exceeds a first threshold voltage	The accused DDR5 RDIMM module allegedly comprises a controller (the PMIC) containing a voltage monitor circuit and nonvolatile memory. The PMIC is alleged to monitor the input voltage, generate a trigger signal on an overvoltage condition, and transmit that signal to other circuitry in the PMIC to perform a write operation to non-volatile memory.	¶¶48-55	col. 25:1-34
a set of components coupled to the PCB, the set of components including a plurality of double data rate (DDR) synchronous dynamic random access memory (SDRAM) devices	The accused DDR5 RDIMM comprises components coupled to the PCB, including DDR5 SDRAM memory devices, a register clock driver (RCD), a PMIC, and temperature sensors.	¶¶56-57	col. 1:45-50
first, second, third, and fourth converter circuits coupled to the PCB and to the input voltage supply line, and configured to receive power from the input voltage supply line and to deliver power via first, second, third, and fourth regulated voltage lines	The PMIC on the accused DDR5 RDIMM allegedly contains circuitry making up four converter circuits that receive power from an input voltage supply line and deliver four regulated voltages to other components on the module. A functional block diagram from a Micron datasheet is provided to show the PMIC delivering multiple voltages (VDDQ, VPP, VDD).	¶¶58-59; ¶61	col. 28:25-41
wherein the plurality of DDR SDRAM devices includes: a first group of at least five DDR SDRAM devices that are each connected to a first chip select line ... a second group of at least four DDR SDRAM devices that are each connected to a second chip select line	The accused 80-bit DDR5 RDIMM module is alleged to have two independent channels (Channel A and Channel B), each with its own chip select signal group. Each channel is alleged to contain at least five SDRAM devices.	¶¶69-72	col. 3:65-67

• Identified Points of Contention:
  • Scope Questions: Claim 1 includes the negative limitation that power from the system board's power rails is "the only power received by the DIMM." This raises the question of how broadly the term "power" will be construed. A defendant may argue that data, address, and control signals also carry some amount of electrical energy, and therefore the accused DIMMs receive more than just power from the designated power rails.
  • Technical Questions: Claim 1 requires the "controller" to perform a specific function: detect an overvoltage condition and, in response, perform a "write operation to write data into the nonvolatile memory." The complaint alleges the PMIC performs this function, but its description states the trigger "would lead to actions that include updating memory spaces in the non-volatile memory." Compl. ¶55 This raises an evidentiary question: does the accused PMIC actually perform this specific, claimed sequence of functions, or is there a mismatch in its technical operation?

V. Key Claim Terms for Construction

• The Term: "the only power received by the DIMM"

• Context and Importance: This negative limitation is critical for infringement. If the defendant can show any other source of electrical energy being "received" by the DIMM, it could defeat the infringement claim. The case may turn on whether "power" is limited to the main operating voltages supplied on the power rails or if it includes any electrical energy, such as that inherent in data and control signals.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: A party might argue that the plain and ordinary meaning of "power" is any electrical energy. The patent does not appear to provide an explicit definition that narrows the term.
  • Evidence for a Narrower Interpretation: A party could argue that the claim preamble distinguishes between a "set of power conduits," a "set of data conduits," and a "set of address and control conduits." Compl. ¶26 This contextual separation suggests the patentee treated the main power supply as functionally distinct from the energy in signal lines, supporting an interpretation that "power" refers only to the supply delivered via the "power conduits."

• The Term: "controller"

• Context and Importance: The complaint identifies the on-module PMIC as the claimed "controller." Compl. ¶49 The viability of this assertion depends on whether a PMIC-a specialized power management chip-can be considered the "controller" as described in the patent, which is required to perform voltage monitoring and a triggered write to non-volatile memory.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patent abstract describes a "voltage monitor circuit" that "produces a signal" when a voltage threshold is exceeded. A party could argue this functional description is consistent with the capabilities of a modern PMIC.
  • Evidence for a Narrower Interpretation: The patent's detailed description illustrates a "CDC" (on-module controller) with complex logic, including a scheduler, DRAM controller, and Flash controller. '366 Patent, Fig. 7 A party may argue that this more sophisticated device is the claimed "controller," and that a standard PMIC, which primarily manages power conversion, lacks the requisite control logic and non-volatile memory write-trigger functionality.

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement under 35 U.S.C. § 271(b), stating that Defendants provide "specifications, datasheets, instruction manuals, and/or other materials that encourage and facilitate infringing uses." Compl. ¶79 It also alleges contributory infringement under § 271(c), asserting the accused products have "no substantial noninfringing uses" and are a "material part of the patented invention." Compl. ¶80
• Willful Infringement: Willfulness is alleged based on Defendants' knowledge of the '366 Patent "since at least the filing of this Complaint." Compl. ¶¶81-82 The claim is based on alleged continued infringement after receiving notice of the patent via the lawsuit.

VII. Analyst's Conclusion: Key Questions for the Case

• A central issue will be one of negative limitation: can Netlist prove that the accused DDR5 DIMMs receive power only from the system board's designated power rails, as strictly required by Claim 1? The outcome may depend on how the court construes the term "power" in contrast to the incidental electrical energy carried by data and control signals.
• A key evidentiary question will be one of functional matching: does the accused on-module PMIC, a specialized power management chip, perform the specific combination of functions required of the claimed "controller"-namely, monitoring voltage and triggering a write to non-volatile memory in response? The case may turn on whether Netlist can show this precise cause-and-effect operation occurs in the accused products, or if a court finds a fundamental mismatch between the accused PMIC and the role of the "controller" as described in the patent's specification.