Netlist Inc v. Samsung Electronics Co Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Netlist, Inc. (Delaware)
  • Defendant: Samsung Electronics Co., Ltd. (Republic of Korea); Samsung Electronics America, Inc. (New York); Samsung Semiconductor, Inc. (California); Avnet, Inc. (New York)
  • Plaintiff's Counsel: McKool Smith, P.C.; Irell & Manella LLP
• Case Identification: 2:25-cv-00748, E.D. Tex., 03/02/2026
• Venue Allegations: Venue is alleged based on Defendants Samsung and Avnet maintaining regular and established places of business within the Eastern District of Texas and having committed acts of infringement in the district.
• Core Dispute: Plaintiff alleges that Defendant's DDR5 memory modules infringe two patents related to on-module power management and timing-controlled data paths in distributed data buffers.
• Technical Context: The technology at issue concerns high-performance Dual In-line Memory Modules (DIMMs), a critical component in servers supporting data-intensive applications like cloud computing and artificial intelligence.
• Key Procedural History: The complaint references a history of litigation between Netlist and Samsung, including prior jury verdicts in the Eastern District of Texas finding infringement of other Netlist patents. It also details a related breach of contract dispute concerning a 2015 Joint Development and License Agreement (JDLA). The complaint notes that Samsung had pre-suit knowledge of the asserted patents, including through an Inter Partes Review (IPR) proceeding Samsung initiated against a patent in the same family as the '366 Patent.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 12,373,366 - "Memory with On-Module Power Management"

• Patent Identification: U.S. Patent No. 12,373,366, titled "Memory with On-Module Power Management," issued on July 29, 2025 (the "'366 Patent").

The Invention Explained

• Problem Addressed: As memory module data rates increase, managing power delivery and voltage control becomes more critical Compl. ¶36 Traditional architectures placed power management circuitry on the computer's main system board (motherboard), which could lead to power loss and less precise voltage control for the memory module itself Compl. ¶36
• The Patented Solution: The invention describes a memory module (DIMM) that integrates power management directly onto its own printed circuit board (PCB) '366 Patent, abstract This is achieved through on-module converter circuits that receive a main input voltage from the system board and generate multiple distinct, regulated voltages required by the various components on the DIMM '366 Patent, abstract The module also includes a controller with a voltage monitor circuit that can detect a trigger condition, such as an overvoltage event, and in response, write data into on-board nonvolatile memory '366 Patent, abstract
• Technical Importance: This on-module power management architecture is a foundational element of the DDR5 memory standard, enabling higher data rates, improved power efficiency, and greater signal integrity compared to prior generations like DDR4 Compl. ¶36

Key Claims at a Glance

The complaint asserts infringement of at least claim 1 Compl. ¶56 The essential elements of independent claim 1 are:

• A dual in-line memory module (DIMM) comprising a printed circuit board (PCB) with specific sets of edge connections for power, data, and address/control signals.
• The power delivered from the system board is the only power received by the DIMM.
• A controller on the PCB that includes a voltage monitor circuit and nonvolatile memory.
• The voltage monitor is configured to monitor an input voltage, generate a trigger signal when the voltage exceeds a threshold, and transmit the signal to the controller.
• The controller is configured to perform a write operation into the nonvolatile memory in response to the trigger signal.
• A set of DDR SDRAM memory devices on the PCB.
• First, second, third, and fourth converter circuits on the PCB that receive power from an input voltage supply line and deliver four regulated voltage lines to various components.
• The SDRAM devices are organized into at least a first group of five or more devices and a second group of four or more devices, each connected to a distinct chip select line.
• The groups of SDRAMs are configured to operate independently to receive or output data in parallel.

U.S. Patent No. 10,268,608 - "Memory Module with Timing-Controlled Data Paths in Distributed Data Buffers"

• Patent Identification: U.S. Patent No. 10,268,608, titled "Memory Module with Timing-Controlled Data Paths in Distributed Data Buffers," issued on April 23, 2019 (the "'608 Patent").

The Invention Explained

• Problem Addressed: In high-speed, high-density memory modules, distributing control and data signals from a central point to numerous memory devices across the module can introduce timing variations (skew) and signal degradation, which compromises system performance and limits operating speed '608 Patent, col. 1:17-38
• The Patented Solution: The patent describes a memory module architecture that uses a plurality of "buffer circuits" distributed across the module board, with each buffer circuit coupled to a corresponding set of memory devices '608 Patent, abstract A central module control device sends command and clock signals to these distributed buffers. Each buffer circuit contains its own command processing circuit and a delay circuit. This allows each buffer to locally "decode the module control signals" and precisely time the flow of data through its data path by using the delay circuit, ensuring proper signal timing for its associated memory devices '608 Patent, col. 2:5-17 '608 Patent, abstract
• Technical Importance: This distributed buffer approach improves signal integrity and timing margins on high-capacity memory modules (such as Load-Reduced DIMMs or LRDIMMs), enabling them to operate at higher speeds and support greater memory densities than would otherwise be possible Compl. ¶16

Key Claims at a Glance

The complaint asserts infringement of at least claim 1 Compl. ¶107 The essential elements of independent claim 1 are:

• A memory module with a module board having edge connections for a memory bus.
• A module control device mounted on the board to receive system commands and output module commands and a module clock.
• Memory devices mounted on the board that receive the module commands and clock to perform memory operations.
• A plurality of buffer circuits, each mounted on the board and coupled between data/strobe signal lines and a corresponding set of memory devices.
• Each buffer circuit includes:
  • A data path for each data signal line.
  • A command processing circuit to decode module control signals and control the data path.
  • At least one tristate buffer within the data path, controlled by the command processing circuit.
  • A delay circuit within the data path, configured to delay a signal by an amount determined by the command processing circuit.

III. The Accused Instrumentality

Product Identification

• The accused products are Samsung's DDR5 memory modules, including, without limitation, DDR5 Registered DIMMs (RDIMMs) and Multiplexed Rank DIMMs (MRDIMMs) Compl. ¶33 Compl. ¶56 Compl. ¶107

Functionality and Market Context

• The accused DDR5 modules represent a major upgrade over the prior DDR4 generation, introducing features such as two independent 40-bit channels (32 data bits plus 8 ECC bits) per module to improve concurrency and bandwidth Compl. ¶35
• A key feature of the accused DDR5 products is the migration of power management from the motherboard onto the module itself via an on-DIMM Power Management Integrated Circuit (PMIC) Compl. ¶36 This PMIC is alleged to be the "controller" recited in the '366 Patent Compl. ¶71
• The accused DDR5 MRDIMMs are a type of high-bandwidth server memory module that uses a Multiplexed Rank Registering Clock Driver (MRCD) and multiple Multiplexed Data Buffers (MDBs) to enable simultaneous access to two ranks of memory, effectively doubling the data rate to the host Compl. ¶110 Compl. ¶111 Compl. ¶117 Compl. ¶123 The complaint alleges the MRCD is the "module control device" and the MDBs are the "buffer circuits" recited in the '608 Patent (Compl. ¶116; Compl. ¶117).
• These products are marketed for use in high-performance servers supporting applications like cloud computing, artificial intelligence, and other data-intensive tasks Compl. ¶27 The complaint includes a screenshot from the website of distributor Avnet advertising a Samsung 128GB DDR5 RDIMM for sale Compl. p. 7

IV. Analysis of Infringement Allegations

'366 Patent Infringement Allegations

'608 Patent Infringement Allegations

Identified Points of Contention

• '366 Patent: A potential point of dispute may be whether the "real time status registers" in the accused PMIC qualify as "nonvolatile memory" as required by claim 1, and whether writing a status code to them constitutes the claimed "write operation to write data" Compl. ¶77 Further, the claim requires that power from the system board is the "only power received by the DIMM" (Compl. ¶22, [1a]), which raises a factual question about whether any other power sources, however minor, are present.
• '608 Patent: The infringement analysis will likely focus on the functionality of the accused MDBs. A key question will be whether the MDBs perform the claimed function of a "command processing circuit configured to decode the module control signals" Compl. ¶126 The defense may argue that the MDBs are simple data multiplexers that act on commands from the central MRCD, rather than performing local decoding. The existence and operation of the claimed "tristate buffer" and "delay circuit" within the MDBs will also be central factual questions for the court.

V. Key Claim Terms for Construction

'366 Patent (Claim 1): "controller including a ... nonvolatile memory"

• Context and Importance: The infringement theory hinges on Samsung's PMIC being the claimed "controller" and its status registers being the "nonvolatile memory" Compl. ¶71 Compl. ¶77 The construction of this composite term will be critical to determining if the accused PMIC, a standard component in DDR5 modules, falls within the claim's scope.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification may define "nonvolatile memory" in a broad sense, encompassing any memory type that retains data without power, which could include status registers.
  • Evidence for a Narrower Interpretation: The patent's detailed description or figures may depict the "nonvolatile memory" being used for purposes beyond simple status logging, such as storing configuration data or backup information, potentially suggesting a narrower scope than a status register.

'608 Patent (Claim 1): "command processing circuit configured to decode the module control signals"

• Context and Importance: This term is central to the patent's point of novelty-distributing intelligence to the buffer circuits. Practitioners may focus on this term because infringement depends on whether the accused MDBs perform active "decoding" or merely execute instructions passed from the MRCD.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent states the command processing circuit is "configured to decode module control signals ... and to control the data path" '608 Patent, abstract This could be argued to cover any interpretation of a control signal that results in a change to the data path's operation, such as directing data flow for a read versus a write, as alleged in the complaint Compl. ¶126
  • Evidence for a Narrower Interpretation: The specification may describe "decoding" in the context of interpreting complex, multi-bit commands, which could support an argument that the MDB's alleged function of reacting to simpler control signals (e.g., from a BCOM bus) does not rise to the level of "decoding" as contemplated by the patent.

VI. Other Allegations

Indirect Infringement

• The complaint alleges both induced and contributory infringement for both patents. Inducement is based on Defendants allegedly providing specifications, datasheets, and instruction manuals that encourage and facilitate infringing use by customers Compl. ¶101 Compl. ¶129 Contributory infringement is based on allegations that the accused products are a material part of the invention and have no substantial non-infringing uses Compl. ¶102 Compl. ¶130

Willful Infringement

• Willfulness is alleged for both patents. For the '366 Patent, the complaint alleges Samsung had pre-suit knowledge as early as May 17, 2022, from an IPR it filed, and from actively monitoring Netlist's patent applications Compl. ¶21 Compl. ¶103 For the '608 Patent, pre-suit knowledge is alleged as of August 2, 2021, via access to Netlist's portfolio and related litigation Compl. ¶25 Compl. ¶131 The complaint asserts that Defendants continue to infringe despite a high likelihood that their actions constitute infringement.

VII. Analyst's Conclusion: Key Questions for the Case

This case presents detailed, feature-specific infringement allegations concerning foundational aspects of DDR5 memory module technology. The outcome will likely depend on the court's resolution of several key technical and definitional questions.

• A primary issue will be one of functional mapping: For the '366 Patent, can the standard operations of an on-DIMM PMIC-specifically, detecting an overvoltage condition and logging it in a status register-be mapped to the claim language requiring a "controller" to "perform... a write operation to write data into the nonvolatile memory"?
• A second core issue will be one of architectural interpretation: For the '608 Patent, does the accused MRDIMM's architecture, which pairs a central "smart" MRCD with distributed "dumb" MDBs, infringe claims that require each distributed "buffer circuit" to contain its own "command processing circuit" for "decoding" control signals locally?
• Finally, a key evidentiary question will be one of technical proof: What internal documentation, source code, or testing data will be produced to either confirm or deny the specific allegations regarding the internal operation of the accused PMICs and MDBs, particularly concerning the existence and control of the claimed tristate buffers and delay circuits in the MDBs?