Advanced Integrated Circuit Process LLC v. Taiwan Semiconductor Mfg Co Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Advanced Integrated Circuit Process LLC (Texas)
  • Defendant: Taiwan Semiconductor Manufacturing Company Limited (Taiwan)
  • Plaintiff’s Counsel: Susman Godfrey LLP
• Case Identification: 2:25-cv-00324, E.D. Tex., 03/05/2026
• Venue Allegations: Plaintiff alleges venue is proper because Defendant is a foreign entity not resident in the United States and may therefore be sued in any judicial district. The complaint details Defendant’s extensive business activities in Texas, including the operation of wholly-owned subsidiaries in Austin and Richardson, longstanding customer and development partnerships with Texas-based companies, and targeted marketing and recruitment events within the state.
• Core Dispute: Plaintiff alleges that Defendant’s semiconductor manufacturing processes, and the integrated circuits produced thereby across various technology nodes, infringe four patents related to semiconductor fabrication methods and device structures.
• Technical Context: The dispute centers on fundamental technologies for fabricating modern integrated circuits, including methods to improve reliability in copper interconnects and specific transistor gate structures, which are critical for the performance and yield of advanced semiconductor devices.
• Key Procedural History: The complaint alleges that Defendant had pre-suit knowledge of three of the four asserted patents, citing their appearance as references during the patent prosecution of Defendant's own U.S. patent applications. Such allegations may form the basis for a claim of willful infringement.

Case Timeline

Date	Event
2003-09-26	Earliest Priority Date for U.S. Patent No. 8,329,572
2003-12-03	Earliest Priority Date for U.S. Patent No. 7,439,623
2003-12-03	Earliest Priority Date for U.S. Patent No. 7,632,751
2008-10-21	U.S. Patent No. 7,439,623 Issued
2009-11-03	Alleged Date of Knowledge of the ’751 Patent by TSMC
2009-12-15	U.S. Patent No. 7,632,751 Issued
2010-12-22	Alleged Date of Knowledge of the ’623 Patent by TSMC
2011-03-25	Earliest Priority Date for U.S. Patent No. 8,884,373
2012-12-11	U.S. Patent No. 8,329,572 Issued
2014-11-11	U.S. Patent No. 8,884,373 Issued
2018-02-06	Alleged Date of Knowledge of the ’572 Patent by TSMC
2026-03-05	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,632,751 - "Semiconductor Device Having Via Connecting Between Interconnects"

• Issued: December 15, 2009

The Invention Explained

• Problem Addressed: In semiconductor manufacturing using copper interconnects, holding the device at high temperatures causes vacancies (microscopic voids) in the copper to migrate along stress gradients. When a wide upper interconnect is connected to a narrow vertical via, these vacancies tend to flow from the wide interconnect and accumulate in the small via, which can cause a physical void to form and break the electrical connection, leading to device failure (’623 Patent, col. 1:21 - col. 2:40).
• The Patented Solution: The invention proposes a method of forming a "dummy hole" in the insulating film near the functional via hole during the fabrication process. When conductive material is deposited, this forms a "dummy via" that is connected to the upper interconnect but is electrically non-functional. This dummy via acts as a sink, drawing in vacancies that would otherwise concentrate in the functional via, thereby reducing the stress gradient and preventing the formation of voids that cause device failure (’751 Patent, abstract; ’751 Patent, col. 3:14-19; ’751 Patent, col. 9:18-32).
• Technical Importance: This method provides a structural solution to improve the reliability and manufacturing yield of multilevel copper interconnects, a foundational technology for high-density, high-performance integrated circuits.

Key Claims at a Glance

• The complaint asserts infringement of at least Claim 1 (Compl. ¶62).
• Independent Claim 1 (Method Claim) Elements:
  • (a) forming a first interconnect on a semiconductor substrate;
  • (b) forming a first insulating film on the first interconnect;
  • (c) forming in the first insulating film, a via hole connected to the first interconnect, a dummy hole which is arranged so as to be incapable of having current flow therethrough, and an interconnect trench connected to the via hole and the dummy hole; and
  • (d) depositing a conductive material in the via hole, the dummy hole and the interconnect trench, thereby forming a via, a dummy via and a second interconnect.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 7,439,623 - "Semiconductor Device Having Via Connecting Between Interconnects"

• Issued: October 21, 2008

The Invention Explained

• Problem Addressed: The patent addresses the same technical problem as the ’751 Patent: stress-induced void formation in copper vias due to the migration of vacancies from larger interconnect layers, which compromises device reliability (’623 Patent, col. 1:21 - col. 2:40).
• The Patented Solution: The patent claims the resulting physical structure of the device rather than the method of making it. The claimed device includes a lower and upper interconnect, a functional via connecting them, and a "dummy via" also connected to the upper interconnect. This dummy via is explicitly defined as being arranged so as to be "incapable of having current flow therethrough" and serves to mitigate vacancy accumulation in the functional via. The patent also claims the structure as a "dual damascene structure" (’623 Patent, abstract; ’623 Patent, col. 2:54-65).
• Technical Importance: The claimed structure provides a tangible design feature for enhancing the thermomechanical reliability of integrated circuits that use copper interconnects.

Key Claims at a Glance

• The complaint asserts infringement of at least Claim 1 (Compl. ¶78).
• Independent Claim 1 (Device Claim) Elements:
  • a semiconductor substrate;
  • a first interconnect formed on the semiconductor substrate;
  • a first insulating film formed on the first interconnect;
  • a second interconnect formed on the first insulating film;
  • a via formed through the first insulating film and connecting between the first and second interconnects; and
  • a dummy via connected to the second interconnect,
  • wherein the dummy via is made of a conductive film and is arranged so as to be incapable of having current flow therethrough;
  • the second interconnect and the via form a dual damascene structure, and
  • the second interconnect and the dummy via form a dual damascene structure.
• The complaint does not explicitly reserve the right to assert dependent claims.

Multi-Patent Capsules

• Patent Identification: U.S. Patent No. 8,329,572, "Semiconductor Device and Method for Fabricating the Same," issued December 11, 2012.

• Technology Synopsis: This patent claims a method for fabricating a semiconductor device. The method involves forming a copper interconnect layer, covering it with an oxidation-resistant conductor film (e.g., cobalt), and then using a single-step etch with a photoresist mask to remove portions of two different insulating films above the interconnect to expose the oxidation-resistant film. This process is designed to protect the copper interconnect during fabrication.

• Asserted Claims: At least Claim 1 (Compl. ¶95).

• Accused Features: The complaint alleges that TSMC’s "cobalt capping and photoresist mask method" used in its 3-, 4-, and 5-nanometer FinFET manufacturing processes infringes the ’572 Patent (Compl. ¶102). Specific accused products mentioned are the Apple A15 Bionic and A18 Bionic (Compl. ¶95).

• Patent Identification: U.S. Patent No. 8,884,373, "Semiconductor Device," issued November 11, 2014.

• Technology Synopsis: This patent claims a specific semiconductor device structure comprising first and second "dual-gate electrodes." A dual-gate electrode combines a p-type (e.g., PMOS) and an n-type (e.g., NMOS) gate electrode. The claims focus on the relative impurity concentrations of the silicon films in the different gate electrodes, which is a technique used to control transistor performance characteristics.

• Asserted Claims: At least Claim 1 (Compl. ¶107).

• Accused Features: The complaint alleges that the Qualcomm Snapdragon S4 Plus MSM8960, manufactured using TSMC’s 28-nanometer process node, has a structure that infringes the ’373 Patent (Compl. ¶108).

III. The Accused Instrumentality

Product Identification

The complaint identifies several classes of accused instrumentalities:

• Accused FinFET Products: All semiconductor devices manufactured by TSMC using its 3-, 4-, 5-, 6-, 7-, 10-, 12-, and 16-nanometer FinFET process nodes (Compl. ¶54). The Broadcom BCM6715 is identified as an exemplary product (Compl. ¶53). These products are accused of infringing the ’751 and ’623 Patents.
• Accused 3-, 4-, and 5-Nanometer Products: All semiconductor devices manufactured by TSMC using these specific process nodes, including the Apple A18 Bionic and A15 Bionic (Compl. ¶57). These products are accused of infringing the ’572 Patent.
• Accused 28-Nanometer Products: All products manufactured by TSMC using its 28-nanometer process node, with the Qualcomm Snapdragon S4 Plus MSM8960 identified as an exemplary product (Compl. ¶¶58-60). These products are accused of infringing the ’373 Patent.

Functionality and Market Context

The accused instrumentalities are the semiconductor manufacturing processes practiced by TSMC and the resulting integrated circuits sold to its customers, such as Apple, Broadcom, and Qualcomm (Compl. ¶¶12; Compl. ¶15; Compl. ¶53; Compl. ¶58). The complaint alleges that these devices are incorporated into a wide range of high-volume consumer electronics, such as smartphones, and that TSMC is a "key manufacturing partner" for major technology companies (Compl. ¶11; Compl. ¶15). The complaint highlights TSMC's marketing of its advanced process technologies at a 2024 Technology Symposium in Austin, Texas (Compl. ¶¶24-25). A promotional image for this event explicitly identifies the defendant, "Taiwan Semiconductor Manufacturing Company Limited," as the host (Compl. p.8). The complaint also points to the professional experience of a TSMC employee in Austin, which includes work on "20nm, 16nm, 10nm, 7nm, 5nm and 3nm FinFET process" nodes, as evidence of TSMC's activities in Texas related to the accused technologies (Compl. ¶28; Compl. p.11).

IV. Analysis of Infringement Allegations

U.S. Patent No. 7,632,751 Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
(a) forming a first interconnect on a semiconductor substrate;	The method for fabricating the BCM6715 involves forming a first interconnect with a polysilicon layer on a substrate.	¶65	col. 9:56-59
(b) forming a first insulating film on the first interconnect;	An insulating film made of SiO₂ is formed on the first interconnect.	¶65	col. 9:60-64
(c) forming in the first insulating film, a via hole connected to the first interconnect, a dummy hole which is arranged so as to be incapable of having current flow therethrough, and an interconnect trench connected to the via hole and the dummy hole;	A via hole is formed to the polysilicon layer, and a dummy hole is formed connecting to a floating "dummy interconnect (metal layer)," rendering it incapable of current flow. An interconnect trench connects both holes.	¶¶66-68	col. 9:65 - col. 10:11
(d) depositing a conductive material in the via hole, the dummy hole and the interconnect trench, thereby forming a via, a dummy via and a second interconnect.	Copper is deposited in the via hole, dummy hole, and trench, which forms the final via, dummy via, and second interconnect.	¶69	col. 11:5-20

U.S. Patent No. 7,439,623 Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a semiconductor device comprising: a semiconductor substrate; a first interconnect formed on the semiconductor substrate; a first insulating film formed on the first interconnect; a second interconnect formed on the first insulating film;	The BCM6715 device includes a substrate, a first copper interconnect, a first insulating film (silicon dioxide and silicon nitride), and a second copper interconnect.	¶82	col. 9:18-24
a via formed through the first insulating film and connecting between the first and second interconnects;	A copper via is formed through the insulating film, connecting the first and second copper interconnects.	¶82	col. 9:24-27
a dummy via connected to the second interconnect, wherein the dummy via is made of a conductive film and is arranged so as to be incapable of having current flow therethrough;	The BCM6715 contains a copper dummy via connected to the second interconnect, which is positioned so that current cannot flow through it.	¶¶82-83	col. 9:27-32
the second interconnect and the via form a dual damascene structure, and the second interconnect and the dummy via form a dual damascene structure.	The complaint alleges that in the BCM6715, these components form dual damascene structures.	¶84	col. 1:1-7

Identified Points of Contention

• Evidentiary Questions: The allegations for the '751 and '623 patents rely on the existence of "dummy" structures within the accused products. A central point of contention may be the evidentiary basis for this claim. The question for the court will be what proof the Plaintiff can offer to demonstrate that certain vias are, in fact, "incapable of having current flow therethrough" and are not used for testing, redundancy, or other latent functions (Compl. ¶67; Compl. ¶83).
• Scope Questions: The complaint broadly accuses all FinFET process nodes from 16nm down to 3nm of infringing patents with a 2003 priority date (Compl. ¶73; Compl. ¶86). A potential dispute will be whether the specific fabrication techniques and resulting structures in these highly advanced, three-dimensional FinFET processes are coterminous with the "dual damascene structure" and other features described in the patents, which were filed in an era of planar transistor technology.

V. Key Claim Terms for Construction

• The Term: "dummy hole which is arranged so as to be incapable of having current flow therethrough" (’751 Patent, Claim 1) and "dummy via... arranged so as to be incapable of having current flow therethrough" (’623 Patent, Claim 1).
• Context and Importance: This limitation is the central inventive concept of the '751 and '623 patents. The definition of a "dummy" structure as one that is "incapable of current flow" will be critical to determining infringement. Practitioners may focus on this term because Defendant could argue that the accused structures have some potential electrical function (e.g., for process monitoring, test access, or capacitive coupling) and are therefore not "incapable" of current flow, thus placing them outside the claim scope.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification of the parent ’623 patent defines a dummy via as one that does "not constitute a closed circuit in actual use of a device" (’623 Patent, col. 3:14-19). Plaintiff may argue this supports a construction where the structure is "dummy" if it does not carry a functional signal during the device's normal operation, regardless of other electrical properties.
  • Evidence for a Narrower Interpretation: The embodiments consistently depict the dummy via connecting to a "dummy interconnect" that is a physically isolated, dead-end conductor (e.g., ’623 Patent, FIG. 2B, element 102B). Defendant may cite these embodiments to argue for a narrower construction, requiring complete electrical isolation from any active circuitry, test points, or power planes for a via to be "incapable of having current flow."

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement for all four patents, asserting that TSMC encourages its customers (e.g., Broadcom, Apple, Qualcomm) to use its infringing process nodes and devices through its sales, engineering, and technical marketing efforts to obtain "design wins" (Compl. ¶74; Compl. ¶87; Compl. ¶103; Compl. ¶117). Contributory infringement is alleged for the '623 and '373 patents on the basis that TSMC's products are a material part of the inventions and are not staple articles of commerce (Compl. ¶¶90-91; Compl. ¶¶120-121).
• Willful Infringement: The complaint alleges pre-suit knowledge and willful infringement for the ’751, ’623, and ’572 patents. The basis for these allegations is the citation of these patents as references during the prosecution of TSMC's own U.S. patent applications, with alleged knowledge dating back to 2009, 2010, and 2018, respectively (Compl. ¶75; Compl. ¶92; Compl. ¶104). For the ’373 Patent, knowledge is alleged "since the filing of this complaint," which would only support a claim of post-suit willfulness (Compl. ¶122).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of evidentiary proof: can Plaintiff produce sufficient technical evidence, likely from extensive reverse engineering, to demonstrate that TSMC’s manufacturing processes for products like the BCM6715 create structures that meet the patent’s definition of a "dummy via," specifically one that is "incapable of having current flow therethrough"?
• A key legal question will be one of claim scope: can the term "dual damascene structure," rooted in the patent’s 2003-era technological context, be construed to read on the complex, three-dimensional architectures of TSMC’s modern FinFET process nodes, or is there a fundamental mismatch in technology that places these advanced processes outside the scope of the claims?
• A central question for damages will be one of knowledge and intent: does the citation of a patent during the prosecution of a defendant’s own patent application, as alleged for three of the patents-in-suit, establish the level of pre-suit knowledge required to support a finding of willful infringement?