Monterey Research LLC v. Renesas Electronics Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Monterey Research, LLC (Delaware)
  • Defendant: Renesas Electronics Corporation (Japan); Denso Corporation (Japan); and Denso International America, Inc. (Delaware)
  • Plaintiff's Counsel: Russ August & Kabat
• Case Identification: 2:24-cv-00238, E.D. Tex., 04/10/2024
• Venue Allegations: Plaintiff alleges venue is proper because Defendants Renesas and Denso are foreign corporations, for which venue is appropriate in any judicial district. Venue is also alleged to be proper as to Defendant Denso International America, Inc. due to its permanent and continuous presence and regular and established places of business within the Eastern District of Texas.
• Core Dispute: Plaintiff alleges that Defendants' semiconductor products, including microcontrollers used in the automotive industry, infringe four patents related to non-volatile memory cell operation, system-level reset functions, and mixed-signal microcontroller architecture.
• Technical Context: The technologies at issue concern fundamental aspects of semiconductor memory and processing, including methods for improving the reliability of data storage and erasure, and architectures for integrating analog and digital functions on a single chip, which are critical in the automotive and broader electronics markets.
• Key Procedural History: The complaint alleges a multi-year history of pre-suit communications with Defendant Renesas, beginning in 2017. These communications allegedly included in-person meetings and the presentation of claim charts for U.S. Patent Nos. 6,243,300 and 7,679,968. The complaint further alleges that subsequent communications notified Renesas of infringement of U.S. Patent Nos. 7,089,133 and 7,825,688. These allegations form the basis of the claim for willful infringement.

Case Timeline

Date	Event
2000-02-16	'300 Patent Priority Date
2000-10-26	'688 Patent Priority Date
2001-06-05	'300 Patent Issue Date
2003-09-16	'133 Patent Priority Date
2006-08-08	'133 Patent Issue Date
2007-05-29	'968 Patent Priority Date
2010-03-16	'968 Patent Issue Date
2010-11-02	'688 Patent Issue Date
2017-07-17	Plaintiff and Renesas meeting regarding patent licensing
2017-10-25	Plaintiff and Renesas meeting; claim chart for '968 Patent allegedly presented
2017-12-20	Plaintiff and Renesas meeting; claim chart for '300 Patent allegedly presented
2018-03-07	Plaintiff and Renesas meeting regarding patent licensing
2018-08-07	Plaintiff letter to Renesas alleging infringement of '300 and '968 Patents
2018-09-11	Plaintiff letter to Denso alleging infringement of '300 and '968 Patents
2022-03-01	Plaintiff letter to Renesas alleging infringement of '133 and '688 Patents
2024-04-10	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,243,300 - "Substrate Hole Injection for Neutralizing Spillover Charge Generated During Programming of a Non-Volatile Memory Cell"

• Patent Identification: U.S. Patent No. 6,243,300, "Substrate Hole Injection for Neutralizing Spillover Charge Generated During Programming of a Non-Volatile Memory Cell," issued June 5, 2001 (the "'300 Patent"). Compl. ¶13

The Invention Explained

• Problem Addressed: The patent describes that certain techniques for erasing non-volatile memory cells can create unwanted "spillover electrons" in the memory cell's channel, which can degrade the programmed threshold voltage and slow down the erase process. Compl. ¶28 '300 Patent, col. 12:40-44
• The Patented Solution: The invention proposes a method to counteract these spillover electrons by actively generating "neutralizing holes" in the semiconductor substrate and moving them into the channel. Compl. ¶28 '300 Patent, abstract These holes then "substantially neutraliz[e]" the spillover electrons, which is intended to improve the speed and effectiveness of the erase operation. '300 Patent, abstract '300 Patent, col. 12:45-53
• Technical Importance: This approach was designed to improve the reliability and performance of erase operations in flash memory, a critical factor for the endurance and speed of such devices. '300 Patent, col. 2:14-18

Key Claims at a Glance

• The complaint asserts infringement of claim 1. Compl. ¶30
• Independent Claim 1 of the '300 Patent recites:
  • A method of erasing a memory cell having a specific structure with a channel that has spillover electrons and a charge trapping region;
  • generating neutralizing holes in the substrate;
  • moving the neutralizing holes to the channel; and
  • substantially neutralizing the spillover electrons with the moved neutralizing holes.

U.S. Patent No. 7,679,968 - "Enhanced Erasing Operation for Non-Volatile Memory"

• Patent Identification: U.S. Patent No. 7,679,968, "Enhanced Erasing Operation for Non-Volatile Memory," issued March 16, 2010 (the "'968 Patent"). Compl. ¶14

The Invention Explained

• Problem Addressed: The patent background explains that during an erase operation, capacitive coupling between a memory cell's well and its word line can disrupt the applied voltages. '968 Patent, col. 2:1-11 This disruption can prevent the word line from reaching its intended negative voltage, which may "delay and/or disrupt the erasing operation." Compl. ¶39 '968 Patent, col. 2:7-11
• The Patented Solution: The patent describes a method and system that adjusts the timing of voltage applications to mitigate this disruptive coupling. A negative voltage is first applied to the word line, and only "when the negative voltage reaches a predetermined voltage," a positive voltage is then applied to the well. '968 Patent, abstract This "timing gap" allows the word line voltage to stabilize before the well voltage is applied, ensuring a more effective erase. Compl. ¶41c '968 Patent, col. 4:45-54
• Technical Importance: By managing the timing of voltage application, the invention aims to enable faster and more effective erasing operations in non-volatile memory. '968 Patent, col. 2:40-42

Key Claims at a Glance

• The complaint asserts infringement of claim 1. Compl. ¶41
• Independent Claim 1 of the '968 Patent recites:
  • A semiconductor device comprising a memory cell array with non-volatile memory cells;
  • A negative voltage generating circuit for applying a negative voltage to a word line during an erasing operation; and
  • A positive voltage generating circuit for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage, wherein there is a timing gap between the start of applying the negative voltage and the start of applying the positive voltage.

U.S. Patent No. 7,089,133 - "Method and Circuit for Providing a System Level Reset Function For an Electronic Device"

• Patent Identification: U.S. Patent No. 7,089,133, "Method and Circuit for Providing a System Level Reset Function For an Electronic Device," issued August 8, 2006 (the "'133 Patent"). Compl. ¶15
• Technology Synopsis: The complaint states that conventional integrated circuits had limitations in detecting low voltage conditions, which could lead to data corruption or malfunction. Compl. ¶50 The '133 Patent is alleged to overcome these issues by teaching a multi-stage reset methodology, which combines an initial, less-precise reset function with a subsequent, tunable, high-precision reset function that becomes active after the device has stabilized. Compl. ¶51
• Asserted Claims: The complaint asserts infringement of claim 1. Compl. ¶53
• Accused Features: The complaint alleges that the power-on reset circuits within various Renesas microcontrollers, including the M16C family, RA 6 Series, and RL78 MCUs, practice the claimed multi-stage reset method. Compl. ¶¶52-53

U.S. Patent No. 7,825,688 - "Programmable Microcontroller Architecture (Mixed Analog/Digital)"

• Patent Identification: U.S. Patent No. 7,825,688, "Programmable Microcontroller Architecture (Mixed Analog/Digital)," issued November 2, 2010 (the "'688 Patent"). Compl. ¶16
• Technology Synopsis: The complaint explains that pre-existing microcontrollers often used separate, pre-programmed, and non-dynamic analog and digital circuits. Compl. ¶62 The '688 Patent allegedly teaches a programmable System-on-a-Chip (SoC) architecture that integrates programmable analog blocks, programmable digital blocks, and a programmable interconnect structure on a single semiconductor chip, allowing for dynamic reconfiguration. Compl. ¶63
• Asserted Claims: The complaint asserts infringement of claim 1. Compl. ¶65
• Accused Features: The complaint alleges that Renesas RH850 Microcontrollers infringe by comprising a plurality of analog and digital circuit blocks (e.g., A/D converters and serial interfaces), a bus (P-Bus) to couple them, and a clock to control the data transfer. Compl. ¶65

III. The Accused Instrumentality

• Product Identification: The accused instrumentalities are semiconductor devices, integrated circuits, and products manufactured and sold by Defendant Renesas, which are then incorporated into a wide variety of downstream products by Defendants Denso and Denso International America. Compl. ¶22 Specific examples cited include Renesas RH850, H8SX, M16C, RA6, RX, RL78, and R-Car families of microcontrollers, as well as products containing embedded flash memory made using Renesas' 90 nm, 40 nm, and 28 nm processes. Compl. ¶9a Compl. ¶9c Compl. ¶29 Compl. ¶40
• Functionality and Market Context: The accused products are described as semiconductor devices, particularly microcontrollers, that are designed and marketed for automotive applications. Compl. ¶23 They are integrated by Denso into components ranging from engine control units to in-cabin information and display systems for leading auto manufacturers. Compl. ¶22 The infringement allegations center on the core operational functionalities of these devices, such as the methods for erasing on-chip flash memory, the power-on reset sequences, and the fundamental mixed-signal architecture. Compl. ¶30 Compl. ¶41 Compl. ¶53 Compl. ¶65

IV. Analysis of Infringement Allegations

No probative visual evidence provided in complaint.

'300 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
A method of erasing a memory cell with a substrate that comprises a first region and a second region with a channel therebetween that has spillover electrons and a gate above said channel, and a charge trapping region that contains a first amount of charge...	The Renesas devices contain a substrate with two regions (for a given memory cell) that contain a channel between them, a gate above the channel, and a nitride film charge trapping region which contains trapped electrons in a programmed state until the cell is fully erased.	¶30	col. 4:35-54
...generating neutralizing holes in said substrate;	Holes are generated by applying a large positive pulse to the source line for the memory cell.	¶30	col. 12:45-53
...moving said neutralizing holes to said channel;	They move to the channel in response to the large negative voltage on the memory gate...	¶30	col. 13:1-4
...and substantially neutralizing said spillover electrons with the neutralizing holes moved to said channel.	...and thereby neutralize the spillover electrons.	¶30	col. 13:3-5

• Identified Points of Contention:
  • Technical Question: The complaint alleges that neutralizing holes are generated by applying a pulse to the "source line" Compl. ¶30, whereas the patent specification describes generating these holes by forward biasing the "drain" relative to the gate during an erase cycle '300 Patent, col. 12:45-53 This raises a factual question as to whether the accused products operate as alleged and whether that operation matches the method taught in the patent.
  • Scope Question: A key question for the court may be whether the electrical operations within the accused devices' erase cycle constitute "generating neutralizing holes" and "substantially neutralizing...spillover electrons" as those terms are defined within the context of the '300 Patent.

'968 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a. A memory cell array having a plurality of non-volatile memory cells.	The '968 Accused Products include non-volatile flash memory devices with multiple memory cells for storing data.	¶41a	col. 3:11-15
b. A negative voltage generating circuit for applying a negative voltage to a word line of the memory cell array during an erasing operation...	The '968 Accused Products include a circuit which generates an NHV (Negative High Voltage) to apply to the word line of the memory array during an erasing operation.	¶41b	col. 4:24-29
c. A positive voltage generating circuit for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage, wherein there is a timing gap between a start of the applying the negative voltage and a start of the applying the positive voltage.	The '968 Accused Products include a circuit which generates a PHV (Positive High Voltage) which is applied to the well of the memory cell during an erase operation. The positive voltage is applied when the negative voltage has reached a pre-determined level, and there is a timing gap in the start of application of the positive and negative voltages in the system.	¶41c	col. 4:45-54

• Identified Points of Contention:
  • Technical Question: The claim requires applying the positive well voltage when the negative word line voltage reaches a predetermined value. A central evidentiary question will be whether the control logic in the accused products implements this specific conditional trigger, or if the timing of the voltage applications is controlled by a different mechanism (e.g., a fixed delay).
  • Scope Question: The proper construction of "timing gap" will be a point of focus. The question for the court will be whether this term requires only that the start of the two voltage applications be non-simultaneous, or if the patent's specification and figures limit the term to a more specific sequence where the positive voltage application begins only after the negative voltage has been applied and has reached or stabilized at its target level.

V. Key Claim Terms for Construction

'300 Patent

• The Term: "spillover electrons"
• Context and Importance: The entire purpose of the claimed method is to neutralize "spillover electrons." The infringement case hinges on establishing that the accused products' erase processes address the same phenomenon defined by this term. Practitioners may focus on this term because its definition determines whether the problem solved by the patent is the same problem addressed by the accused devices.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent specification describes "spillover electrons" as a phenomenon that "can degrade the programmed threshold voltage." '300 Patent, col. 12:41-42 This could support an interpretation covering any programming-induced charge in the channel that negatively impacts device performance.
  • Evidence for a Narrower Interpretation: The description connects these electrons to specific programming techniques that "create 'spillover' electrons in the channel." '300 Patent, col. 12:40-41 This may support an argument that the term is limited to electrons generated by the specific hot-electron injection programming methods discussed in the patent's background.

'968 Patent

• The Term: "when the negative voltage reaches a predetermined voltage"
• Context and Importance: This phrase dictates the critical timing and triggering condition for the invention. Infringement depends on whether the accused devices' circuits operate based on this specific conditional logic. Practitioners may focus on this term because it defines the novel sequence of operations at the heart of the claim.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The abstract states the positive voltage is applied "when the negative voltage reaches a predetermined voltage." '968 Patent, abstract This could be argued to encompass any system that sequences the positive voltage application to occur after the negative voltage has reached its target range, regardless of the precise trigger mechanism.
  • Evidence for a Narrower Interpretation: The patent's flowchart in Figure 5 explicitly shows a decision step ("IS NEGATIVE VOLTAGE PREDETERMINED VOLTAGE?") that determines when to proceed. '968 Patent, FIG. 5, step S12 This may support a narrower construction requiring an active voltage monitoring circuit that triggers the next step only upon sensing that a specific voltage level has been met.

VI. Other Allegations

• Indirect Infringement: The complaint alleges both induced and contributory infringement for all asserted patents. Inducement is alleged based on Defendants recommending the normal mode of operation of the accused products to customers and end-users, and by providing materials like user manuals and product documentation. Compl. ¶23 Compl. ¶32 Compl. ¶43 Compl. ¶55 Compl. ¶67 Contributory infringement is alleged on the basis that the accused products are a material part of the inventions and are not staple articles of commerce suitable for substantial noninfringing use. Compl. ¶33 Compl. ¶44 Compl. ¶56 Compl. ¶68
• Willful Infringement: The complaint alleges willful infringement for all four patents based on pre-suit knowledge. It alleges Renesas was aware of the '968 Patent since at least October 25, 2017, and the '300 Patent since at least December 2017, from meetings where claim charts were allegedly presented. Compl. ¶25a Compl. ¶42 Compl. ¶47 Knowledge of the '133 and '688 patents is alleged since at least March 1, 2022, from a letter sent to Renesas. Compl. ¶54 Compl. ¶66 The complaint alleges that despite this knowledge, Defendants continued to infringe, rendering their actions knowing, deliberate, and egregious. Compl. ¶36 Compl. ¶47 Compl. ¶59 Compl. ¶71

VII. Analyst's Conclusion: Key Questions for the Case

• A central issue will be one of factual correspondence and claim construction: Do the operational cycles of the accused microcontrollers, as a matter of technical fact, align with the specific method steps and circuit functions recited in the asserted claims? This will involve construing key terms like "spillover electrons" ('300 Patent) and "timing gap" ('968 Patent) and determining if the accused devices' functions fall within the scope of those constructions.
• A key evidentiary question will concern willfulness: The complaint alleges a detailed history of pre-suit notice, including the presentation of claim charts for two of the patents. The case may turn on what was communicated in those interactions and whether Defendants' subsequent actions rise to the level of egregious conduct sufficient to support enhanced damages.
• For the system-level patents ('133 and '688), a core question will be one of inventive concept versus conventional design: Do the accused microcontrollers, which combine various circuit elements like power-on-reset blocks, ADCs, and digital logic, merely implement a conventional arrangement of known components, or is their specific architecture and multi-stage operational logic an implementation of the novel system-level methods claimed in the '133 and '688 patents?