Eireog Innovations Ltd v. Cisco Systems Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: EireOg Innovations Limited (Ireland)
  • Defendant: Palo Alto Networks, Inc. (Delaware)
  • Plaintiff's Counsel: BC LAW GROUP, P.C.
• Case Identification: 2:24-cv-00227, E.D. Tex., 02/26/2025
• Venue Allegations: Venue is alleged to be proper based on Defendant being registered to do business in Texas, transacting business in the district, and having a regular and established place of business in Plano, Texas.
• Core Dispute: Plaintiff alleges that Defendant's Next-Generation Firewall products, which incorporate specific Intel and AMD central processing units (CPUs), infringe four patents related to processor interrupt management and cache processing.
• Technical Context: The patents address low-level processor architecture features for managing interrupts in virtualized environments and optimizing cache performance, technologies fundamental to modern high-performance computing and networking appliances.
• Key Procedural History: The complaint is part of a multi-defendant litigation, with this case designated as a "Member Case" in a lead case against Cisco Systems, Inc.

Case Timeline

Date	Event
2009-05-07	U.S. Patent No. 8,117,399 Priority Date
2010-09-21	U.S. Patent No. 8,504,777 Priority Date
2012-02-14	U.S. Patent No. 8,117,399 Issues
2012-08-09	U.S. Patent No. 9,436,626 Priority Date
2012-08-09	U.S. Patent No. 9,442,870 Priority Date
2013-08-06	U.S. Patent No. 8,504,777 Issues
2016-09-06	U.S. Patent No. 9,436,626 Issues
2016-09-13	U.S. Patent No. 9,442,870 Issues
2025-02-26	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,436,626 - Processor interrupt interface with interrupt partitioning and virtualization enhancements

The Invention Explained

• Problem Addressed: In data processing systems with multiple processors or virtualized partitions, interrupt processing can be delayed as different processes compete for access to a central interrupt controller. Conventional mechanisms that manage interrupt priority on a per-processor basis do not adequately address the needs of partitioned or virtualized systems ʼ626 Patent, col. 1:12-32
• The Patented Solution: The invention proposes a processor-based interrupt management system where interrupt requests are delivered to the processor core along with context information, including a partition identifier (LPID), thread identifier (VPID), and priority level ʼ626 Patent, col. 2:17-34 This allows the processor core itself, using special purpose registers, to determine if an interrupt should be taken by the correct partition without needing to consult an external controller or requiring intervention from a hypervisor, thereby reducing latency ʼ626 Patent, col. 5:1-35
• Technical Importance: This architecture enables more efficient and direct interrupt handling in complex, virtualized, and multi-threaded environments, which is critical for performance-sensitive applications like network security.

Key Claims at a Glance

• The complaint asserts at least independent claim 1 Compl. ¶10
• The essential elements of independent claim 1 include:
  • receiving at the processor an interrupt package provided by an interrupt controller, where the package comprises a first interrupt request, an interrupt identifier, a partition identifier, a priority value, and a thread identifier;
  • processing the interrupt package against one or more partitions running on the processor by comparing the priority value and partition identifier against at least a stored priority level and stored partition identifier retrieved from special purpose registers at the processor; and
  • to determine on a partition basis if the first interrupt request is blocked or forwarded to a targeted thread identified by the thread identifier.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 9,442,870 - Interrupt priority management using partition-based priority blocking processor registers

The Invention Explained

• Problem Addressed: As with the ʼ626 Patent, the background describes the performance issues in managing interrupts in partitioned or virtualized systems, where access times to a central interrupt controller create bottlenecks ʼ870 Patent, col. 1:19-27
• The Patented Solution: The patent discloses a processor core architecture with special purpose registers that control interrupt priority blocking on a partition-by-partition basis ʼ870 Patent, col. 2:1-10 A received interrupt's partition identifier (LPID) is used to select the appropriate priority register on the processor core itself. The interrupt's priority level is then compared against the value in that register to determine if the interrupt should be blocked or forwarded to the virtual processor, simplifying the external interrupt controller's design ʼ870 Patent, col. 2:10-24
• Technical Importance: By moving partition-based blocking logic onto the processor core, this invention aims to reduce latency and software complexity associated with managing interrupts in multi-partition systems.

Key Claims at a Glance

• The complaint asserts at least independent claim 1 Compl. ¶20
• The essential elements of independent claim 1 include:
  • receiving at the processor an interrupt package for a first physical interrupt request, where the package comprises a first priority value and a first partition identifier; and
  • processing the interrupt package against one or more partitions by comparing the first priority value and first partition identifier against at least a stored priority level and stored partition identifier retrieved from one or more special purpose registers at the processor;
  • to determine on a partition basis if the first physical interrupt request is blocked or forwarded to a targeted virtual processor.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 8,504,777 - Data processor for processing decorated instructions with cache bypass

• Technology Synopsis: The patent describes a method for handling "decorated instructions," which are instructions that include an additional command for a target memory device. To prevent the processor's cache from holding stale data after the memory device modifies a value, decorated instructions designated for "cache bypass" cause any corresponding cache entry to be invalidated upon a cache hit, forcing the operation to be completed directly on the target memory ʼ777 Patent, abstract ʼ777 Patent, col. 2:47-67
• Asserted Claims: The complaint asserts at least independent claim 16 Compl. ¶30
• Accused Features: The "accused cache processing features" of Defendant's products are alleged to infringe Compl. ¶33

U.S. Patent No. 8,117,399 - Processing of coherent and incoherent accesses at a uniform cache

• Technology Synopsis: The patent discloses a method for managing a unified cache that stores both data and instructions. Each cache line is marked as "coherent" or "incoherent." A coherent read access that hits an incoherent cache line is treated as a cache miss, triggering a broader "global snoop" to ensure data integrity. In contrast, an incoherent read access can hit on either type of cache line, and a resulting miss may trigger a more limited "non-global snoop." This allows instruction fetches, which are often read-only, to be treated as incoherent, reducing system interconnect traffic ʼ399 Patent, abstract ʼ399 Patent, col. 1:50-col. 2:10
• Asserted Claims: The complaint asserts at least independent claim 14 Compl. ¶40
• Accused Features: The "accused cache processing features" of Defendant's products are alleged to infringe Compl. ¶43

III. The Accused Instrumentality

Product Identification

The accused products are Palo Alto Networks ("PAN") Next-Generation Firewalls that incorporate specific CPU architectures Compl. ¶9 Compl. ¶19 Compl. ¶29 Compl. ¶39

Functionality and Market Context

The complaint identifies two categories of CPUs used in the accused firewalls: Intel-based CPUs (Haswell, Skylake, and newer architectures) and AMD-based CPUs (Zen and EPYC architectures) Compl. ¶9 Compl. ¶19 Compl. ¶29 Compl. ¶39 The complaint alleges that these firewalls, including specific models like the PA-5220, PA-5450, and others, use the accused CPU features to perform their functions Compl. ¶9 Compl. ¶19 Compl. ¶29 Compl. ¶39 The complaint references marketing materials that promote the benefits of using these advanced processors for "next-gen security services" Compl. ¶12 For example, a marketing presentation referenced in the complaint highlights the use of these processors for security services with inline AI inference Compl. ¶12 Compl. ¶22 The complaint also points to hardware installation guides as evidence of how customers are instructed to use the accused functionality Compl. ¶12 Compl. ¶22

IV. Analysis of Infringement Allegations

The complaint states that claim charts demonstrating infringement of the asserted patents are attached as exhibits Compl. ¶10 Compl. ¶20 Compl. ¶30 Compl. ¶40 However, these exhibits were not provided. The infringement theory is therefore summarized based on the complaint's narrative allegations.

'626 Patent Infringement Allegations

The complaint alleges that Defendant's Accused Products, which use certain Intel and AMD CPUs, directly infringe one or more claims of the '626 Patent Compl. ¶9 The core allegation is that the interrupt management features within these CPUs practice the claimed invention related to interrupt partitioning and virtualization enhancements Compl. ¶13 The complaint asserts this infringement theory is detailed in Exhibits 2 and 3, which were not available for analysis.

• Identified Points of Contention:
  • Scope Questions: A central question may be whether the term "interrupt package" as claimed, which includes a specific combination of identifiers (interrupt, partition, thread) and values (priority), reads on the precise data structures transmitted between the interrupt controller and processor core in the accused CPUs. The defense may argue for a narrow interpretation of the required package contents.
  • Technical Questions: A key factual dispute may concern the function of the "special purpose registers" on the accused CPUs. The court will need to determine if these registers are used to perform the claimed comparison of partition identifiers and priority levels to decide whether an interrupt is "blocked or forwarded" in the specific manner required by the claim.

'870 Patent Infringement Allegations

The complaint alleges that the same set of Accused Products infringes the '870 Patent Compl. ¶19 The infringement theory centers on the "accused processor interrupt management features," which allegedly embody the claimed invention of using "partition-based priority blocking processor registers" Compl. ¶23 This theory is purportedly detailed in the unprovided Exhibits 7 and 8.

• Identified Points of Contention:
  • Scope Questions: The case may turn on the construction of "partition-based priority blocking." The patent describes a system where this blocking is performed at the processor core itself, reducing the complexity of the external interrupt controller. A question is whether the accused CPUs implement this specific architectural division of labor.
  • Technical Questions: Evidence will be required to show that the accused CPUs perform interrupt blocking "on a partition basis" as claimed. This raises the question of whether the CPU's priority mechanism is merely a general-purpose system or if it specifically uses a "partition identifier" to select among different sets of blocking rules for different virtualized environments, as the patent appears to require.

V. Key Claim Terms for Construction

For the '626 Patent

• The Term: "special purpose registers" (from Claim 1)
• Context and Importance: This term is the locus of the claimed decision-making logic. The infringement analysis depends on whether the accused CPUs contain registers that meet this definition and perform the claimed comparison function. Practitioners may focus on this term because its scope will determine what kind of hardware evidence is required to prove infringement.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim language itself does not limit the registers to a specific type or name, only to their function of being used for the comparison. This may support an interpretation that any registers used for this purpose, regardless of their other functions, qualify.
  • Evidence for a Narrower Interpretation: The specification provides specific examples of such registers, including "LPID registers 35," "INTLEVEL registers 36," "external proxy registers (EPR) 37," and "external process ID registers (EPIDR) 38" ʼ626 Patent, col. 5:4-14 A defendant may argue these examples limit the term's scope to registers with these specific roles in managing partition, priority, and vector information.

For the '870 Patent

• The Term: "processing the interrupt package against one or more partitions" (from Claim 1)
• Context and Importance: This phrase defines the core action of the invention. The dispute will likely center on whether the accused CPUs perform an operation that can be characterized as processing "against" a "partition." The definition of these actions is critical to mapping the claim onto the accused functionality.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: Claim 1 describes this "processing" as "comparing the first priority value and first partition identifier against... a stored priority level and stored partition identifier." This functional language could be argued to cover any system that uses both a priority and a partition ID as inputs to an interrupt blocking decision.
  • Evidence for a Narrower Interpretation: The specification describes a specific flow where the received LPID is first compared to a stored LPID in an LPIDR register to determine if the interrupt is for the hypervisor, an active guest, or an inactive guest, which then dictates which priority register (INTLEVEL or GINTLEVEL) is used for the subsequent comparison ʼ870 Patent, col. 8:1-24 This detailed implementation could support a narrower, multi-step definition of "processing... against... partitions."

VI. Other Allegations

• Indirect Infringement: The complaint alleges both induced and contributory infringement for all four patents. For inducement, Plaintiff alleges Defendant provides "user manuals and online instruction materials" that instruct customers on how to "setup, configure, and utilize the Accused Products" in an infringing manner Compl. ¶12 Compl. ¶22 Compl. ¶32 Compl. ¶42 For contributory infringement, Plaintiff alleges the "accused processor interrupt management features" and "accused cache processing features" are a material part of the inventions, are especially made or adapted for infringement, and are not staple articles of commerce suitable for non-infringing use Compl. ¶13 Compl. ¶23 Compl. ¶33 Compl. ¶43
• Willful Infringement: The complaint does not use the word "willful," but it establishes a basis for post-suit willfulness by alleging that Defendant has knowledge of the patents and their infringement "At least as of the filing and service of this complaint... through, for example, the... Patent claim charts served therewith" Compl. ¶12 Compl. ¶13 Compl. ¶22 Compl. ¶23

VII. Analyst's Conclusion: Key Questions for the Case

The resolution of this dispute will likely depend on the court's findings on a few central issues that bridge claim construction and technical evidence:

1. A core issue will be one of architectural mapping: Do the accused Intel and AMD CPUs implement the specific partition-based interrupt-handling architecture described in the '626 and '870 patents? This will require a detailed technical comparison between the patent's description of on-core registers (e.g., LPIDR, INTLEVEL) managing distinct hypervisor and guest priority levels, and the actual microarchitecture of the accused processors.
2. A second key question will be one of functional equivalence in cache management: Do the cache mechanisms in the accused CPUs perform the specific operations required by the '777 and '399 patents? For the '777 patent, this involves determining if the CPUs execute "decorated instructions" that bypass the cache in the claimed manner. For the '399 patent, it involves assessing whether the CPUs use a "coherent/incoherent" marking system for a unified cache that treats a coherent read to an incoherent line as a miss.
3. A determinative legal question will be one of definitional scope: Can terms rooted in the patent's specific embodiments, such as "special purpose registers" ('626 patent) and "processing...against one or more partitions" ('870 patent), be construed broadly enough to read on the general-purpose, highly complex interrupt and cache systems of modern commercial CPUs, or are the claims limited to the precise implementations disclosed?