MOSAID Tech Inc v. Intel Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: MOSAID Technologies Inc. (Canada)
  • Defendant: Intel Corporation (Delaware)
  • Plaintiff's Counsel: Ciccarelli Law Firm; Winstead PC
• Case Identification: 1:25-cv-677, W.D. Tex., 05/06/2025
• Venue Allegations: Venue is asserted based on Defendant's alleged commission of infringing acts within the Western District of Texas and its maintenance of regular and established places of business in the District, including a research and development campus in Austin employing over 1,400 individuals.
• Core Dispute: Plaintiff alleges that Defendant's semiconductor devices, manufactured using various advanced process nodes, infringe eleven patents related to semiconductor circuit layout, transistor structure, and manufacturing methods.
• Technical Context: The patents relate to fundamental aspects of modern semiconductor design and fabrication, including techniques to manage layout-dependent electrical effects, optimize transistor interconnects, and enhance performance using mechanical stress and FinFET architectures.
• Key Procedural History: The complaint asserts a large portfolio of patents, many of which are divisionals or continuations of one another, suggesting a focused and long-term research and development effort in specific areas of semiconductor technology. No prior litigation or post-grant proceedings are mentioned in the complaint.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,476,957 - "Semiconductor Integrated Circuit,"

• Issued: January 13, 2009

The Invention Explained

• Problem Addressed: In miniaturized integrated circuits, the electrical characteristics of a transistor (such as its threshold voltage) can be undesirably altered by its proximity to the boundary of its "well," a phenomenon known as the "well proximity effect." This effect varies with the transistor's layout and size, complicating circuit simulation and potentially degrading performance ʼ957 Patent, col. 1:29-55
• The Patented Solution: The invention proposes a layout methodology to counteract this variability. For multiple transistors of different sizes within the same well, their active regions are positioned such that the distance from the well boundary to the center point of each active region is "substantially the same." By equalizing this distance, the invention seeks to make the well proximity effect uniform across the transistors, thereby improving simulation accuracy and design predictability ʼ957 Patent, abstract ʼ957 Patent, col. 3:1-11 Figure 1 illustrates this principle with equations defining the alignment of the active regions' center locations relative to the well boundary ʼ957 Patent, FIG. 1
• Technical Importance: This layout technique provided a structural solution to a significant electrical modeling problem in advanced semiconductor nodes, aiming to improve design reliability without increasing simulation time or cost ʼ957 Patent, col. 2:56-62

Key Claims at a Glance

• The complaint asserts infringement of at least independent claim 1 Compl. ¶103
• Claim 1 Elements:
  • A semiconductor integrated circuit comprising a substrate with first and second well regions of different conductivity types in contact at a well boundary.
  • A first active region of a second conductivity type within the first well region.
  • A second active region of the second conductivity type within the first well region, differing in length (in the gate width direction) from the first active region.
  • The distance from the well boundary to the halfway point of the first active region's length is "substantially the same" as the distance from the well boundary to the halfway point of the second active region's length.

U.S. Patent No. 7,514,757 - "Memory Formation with Reduced Metallization Layers,"

• Issued: April 7, 2009

The Invention Explained

• Problem Addressed: The fabrication of high-density memories, such as Static Random-Access Memory (SRAM), conventionally required three or more metal layers for routing. Furthermore, the long vertical contact plugs connecting the first metal layer down to the transistor source/drain regions contributed to performance-degrading parasitic capacitance and RC delay ʼ757 Patent, col. 1:24-38
• The Patented Solution: The patent describes a semiconductor structure that reduces metallization complexity. It introduces a "first-layer contact" for local interconnections within an SRAM cell, which is formed in a "lower portion" of the inter-layer dielectric (ILD) that sits below the first main metallization layer. This isolates local cell wiring from global routing, potentially reducing the number of metal layers required and shortening contact paths to improve electrical performance ʼ757 Patent, abstract ʼ757 Patent, col. 2:47-67
• Technical Importance: This architecture aimed to reduce manufacturing costs and complexity for embedded SRAM while simultaneously improving device speed by mitigating parasitic effects associated with long interconnects ʼ757 Patent, col. 2:30-34

Key Claims at a Glance

• The complaint asserts infringement of at least independent claim 1 Compl. ¶118
• Claim 1 Elements:
  • A semiconductor structure with an SRAM cell (comprising pull-up, pull-down, and pass-gate MOS devices).
  • A first metallization layer.
  • An inter-layer dielectric (ILD) underlying the first metallization layer, where the ILD has an upper and lower portion.
  • A "first first-layer contact" located in the lower portion of the ILD, connecting at least two of the SRAM cell's MOS devices, and which is "physically isolated" from additional contacts in the upper ILD portion.
  • A second first-layer contact also in the lower portion of the ILD.
  • A second-layer contact positioned on the second first-layer contact, connecting it to a bit-line or power line.

U.S. Patent No. 9,349,655 - "Method for Mechanical Stress Enhancement in Semiconductor Devices,"

• Issued: May 24, 2016
• Technology Synopsis: The patent describes an integrated circuit structure that uses "dummy gates" placed at the sides of an operational device to enhance mechanical stress in the device's strained channel, a technique used to improve transistor performance ʼ655 Patent, abstract
• Asserted Claims: At least independent claim 1 is asserted Compl. ¶133
• Accused Features: The complaint alleges that instrumentalities made using Intel's 10 nm or Intel 7 fabrication processes incorporate the claimed dummy gate structures Compl. ¶131

The FinFET Family (U.S. Patent Nos. 8,809,940; 8,440,517; 9,209,300; 9,379,215; 9,716,091)

• Technology Synopsis: This family of patents describes structures and fabrication methods for FinFETs, which are non-planar transistors central to modern semiconductor nodes. The inventions focus on the geometry of the transistor "fin," the surrounding insulation regions (e.g., forming "tapered top surfaces"), and the integration of strained materials to enhance performance ʼ940 Patent, abstract ʼ517 Patent, abstract
• Asserted Claims: The complaint asserts at least claim 1 of the ʼ940 Patent Compl. ¶149; claim 1 of the ʼ517 Patent Compl. ¶164; claim 1 of the ʼ300 Patent Compl. ¶176; claim 1 of the ʼ215 Patent Compl. ¶191; and claim 11 of the ʼ091 Patent Compl. ¶203
• Accused Features: The complaint alleges that instrumentalities made using Intel's 22FFL, Intel 16, Intel 3, or Intel 4 fabrication processes incorporate the claimed FinFET structures and are made by the claimed methods Compl. ¶147 Compl. ¶162 Compl. ¶174 Compl. ¶189 Compl. ¶201

The Two-Step STI Family (U.S. Patent Nos. 7,842,577; 8,338,909)

• Technology Synopsis: The patents describe a method of forming isolation structures in an integrated circuit using a "two-step" process. A first isolation region is formed before the MOS device, and a second isolation region is formed after, by etching a portion of the source/drain region to create a trench that is then filled with a dielectric ʼ577 Patent, abstract
• Asserted Claims: At least claim 1 of the ʼ577 Patent Compl. ¶218 and claim 1 of the ʼ909 Patent Compl. ¶230 are asserted.
• Accused Features: The complaint alleges that instrumentalities made using Intel's 10 nm, Intel 7, Intel 4, or Intel 3 fabrication processes are made by the claimed methods and incorporate the resulting structures Compl. ¶216 Compl. ¶228

U.S. Patent No. 9,564,433 - "Semiconductor Device with Improved Contact Structure and Method of Forming the Same,"

• Issued: February 7, 2017
• Technology Synopsis: The patent describes a method for forming a contact structure in a MOS transistor. It involves forming a first, elongated contact over the source/drain feature and then forming a second, different-sized contact over both the first contact and the gate stack, creating a specific multi-part, overlapping contact geometry ʼ433 Patent, abstract
• Asserted Claims: At least independent method claim 8 is asserted Compl. ¶244
• Accused Features: The complaint alleges that instrumentalities made using Intel's 10 nm and Intel 7 fabrication processes are made by the claimed methods Compl. ¶242

III. The Accused Instrumentality

Product Identification

The complaint identifies the "Accused Instrumentalities" as a wide range of semiconductor devices manufactured by Intel, including processors, graphics chips (GPUs), chipsets, FPGAs, and server products Compl. ¶8 These devices are alleged to be made using Intel's 22FFL, Intel 16, Intel 10 nm, Intel 7, Intel 4, and Intel 3 process nodes Compl. ¶8 Specific product families named include Intel Core (e.g., Cannon Lake, Ice Lake, Alder Lake, Meteor Lake), Xeon (e.g., Sapphire Rapids), and Atom processors Compl. ¶¶10-13 The allegations also extend to devices manufactured for third-party "Intel Foundry Customers" Compl. ¶14

Functionality and Market Context

The accused products are the central processing units and related components that power a vast array of electronic devices, from servers to consumer laptops and desktops Compl. ¶15 The complaint alleges that Intel's Process-Design Kits (PDKs) and collaboration with Electronic-Design-Automation (EDA) tool vendors enforce design rules that result in the manufacture of chips with the allegedly infringing physical structures Compl. ¶16 Compl. ¶99 Intel is positioned in the complaint as a major market participant that sells these components to large-scale customers, such as Dell Technologies, and through distributors Compl. ¶87 Compl. ¶94

No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint references claim chart exhibits that are not provided. The following summary is based on the narrative infringement theories and claim language presented in the complaint.

U.S. Patent No. 7,476,957 Infringement Allegations

• Identified Points of Contention:
  • Scope Questions: A central issue will be the construction of "substantially the same." The infringement analysis will likely turn on whether the degree of geometric alignment present in Intel's actual layouts, which may have some manufacturing-related variance, falls within the scope of this term as defined by the patent.
  • Technical Questions: A key factual question is whether Intel's design rules for its advanced nodes are driven by the specific "halfway point" alignment principle taught in the ʼ957 patent, or by other, more complex layout-dependent effect compensation models that may achieve a similar result through different means.

U.S. Patent No. 7,514,757 Infringement Allegations

• Identified Points of Contention:
  • Scope Questions: The analysis may focus on the definition of an ILD having distinct "upper" and "lower" portions. How this structural boundary is defined will be critical to determining if the accused "first-layer contact" resides solely in the "lower portion" as required.
  • Technical Questions: An evidentiary question will be whether the accused contact is truly "physically isolated" from contacts in the upper ILD portion. This will require detailed structural analysis of the accused chips to determine if the contacts are discrete structures as claimed, or part of a more integrated, unitary contact plug structure that extends through multiple dielectric layers.

V. Key Claim Terms for Construction

For the '957 Patent

• The Term: "substantially the same"
• Context and Importance: This term is the central limitation of claim 1. Its construction will determine the permissible deviation in the alignment of the active regions' center points. A narrow interpretation requiring near-perfect geometric alignment could make infringement difficult to prove, while a broader, more functional interpretation focused on achieving a comparable electrical effect could expand the claim's scope.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent's objective is to prevent the influence of the well proximity effect from varying, which suggests a functional rather than purely geometric identity ʼ957 Patent, col. 3:12-19
  • Evidence for a Narrower Interpretation: Figure 1 of the patent presents a precise mathematical equation (STIp1+0.5Wp1 = STIp2+0.5Wp2) to define the alignment, which may support an argument for a narrow, quantitative interpretation of the term ʼ957 Patent, FIG. 1 ʼ957 Patent, col. 5:40-44

For the '757 Patent

• The Term: "lower portion of the ILD"
• Context and Importance: This term defines the location of the novel "first-layer contact." The infringement analysis hinges on whether the accused device's dielectric can be conceptually and physically divided into an "upper" and "lower" portion, and whether the accused contact is confined to the latter.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification introduces the concept of an ILD with upper and lower portions without providing a strict, universal definition or manufacturing process for creating such a boundary, which may suggest a more flexible interpretation based on the overall structure ʼ757 Patent, col. 2:53-56
  • Evidence for a Narrower Interpretation: Figure 4 clearly depicts the ILD 24 as being composed of two distinct layers, 24₁ and 24₂, with the first-layer contact 28 residing entirely within the lower layer 24₁. This specific embodiment may be used to argue that the "lower portion" must be a structurally distinct layer ʼ757 Patent, FIG. 4 ʼ757 Patent, col. 4:45-50

VI. Other Allegations

• Indirect Infringement: The complaint alleges inducement of infringement against Intel for providing customers, including foundry partners, with instructive materials such as Process Design Kits (PDKs), technical support, and EDA tools that allegedly direct and require users to design and manufacture products that infringe the asserted patents Compl. ¶¶106-107 Contributory infringement is alleged on the basis that the accused processors have no substantial non-infringing uses and are a material part of the patented inventions Compl. ¶¶111, 126
• Willful Infringement: The complaint alleges willful infringement based on Intel's continued infringement after having "express and actual knowledge" of the patents and their infringement, with knowledge alleged to exist "no later than the date of filing of this Complaint" Compl. ¶¶108, 113

VII. Analyst's Conclusion: Key Questions for the Case

1. A core issue will be one of definitional scope: can terms rooted in the context of older process technologies, such as "substantially the same" distance ('957 patent) or a distinct "lower portion of the ILD" ('757 patent), be construed to read on the highly complex, three-dimensional structures and layout rules of Intel's modern FinFET processes?

2. A central evidentiary question will be one of structural correspondence: does a physical, layer-by-layer analysis of Intel's accused processors reveal the specific geometric layouts, multi-part contact structures, and material arrangements required by the patent claims, or do Intel's devices achieve similar technical goals through fundamentally different and non-infringing structures?

3. A significant challenge will be the apportionment of damages: if infringement is found on any of the eleven asserted patents, which cover discrete and granular aspects of semiconductor design, a key question for the court will be how to value the contribution of those specific features to a multifaceted and highly valuable end product like a modern Intel processor.