Signal LLP v. Ambarella Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Signal, LLP (Nevada)
  • Defendant: Ambarella, Inc. (Delaware)
  • Plaintiff's Counsel: Standley Law Group LLP
• Case Identification: 3:26-cv-00152, S.D. Ohio, 05/22/2026
• Venue Allegations: Venue is based on Defendant maintaining a regular and established place of business in the district, specifically a research and development facility in Beavercreek, Ohio.
• Core Dispute: Plaintiff alleges that Defendant's semiconductor products, which include memory controllers for various DDR memory standards, infringe five U.S. patents related to on-die termination control and write-data error correction.
• Technical Context: The technology at issue concerns high-speed memory interfaces, a critical component in modern electronics, where managing signal integrity and data accuracy is essential for performance and reliability.
• Key Procedural History: The complaint asserts that Defendant had pre-suit knowledge of the patents based on a November 15, 2022 notice of infringement from Plaintiff's predecessor-in-interest, Rambus Inc. This notice allegedly included claim charts for at least two of the asserted patents and forms the primary basis for the willful infringement allegations. The patents were assigned from Rambus to Signal on September 29, 2025.

Case Timeline

Date	Event
2006-01-11	'352 Patent Priority Date
2006-06-02	'400 Patent Priority Date
2006-06-02	'902 Patent Priority Date
2006-12-21	'962 Patent Priority Date
2006-12-21	'439 Patent Priority Date
2015-02-03	'962 Patent Issue Date
2015-07-28	'352 Patent Issue Date
2018-08-21	'902 Patent Issue Date
2018-10-30	'439 Patent Issue Date
2021-03-09	'400 Patent Issue Date
2022-11-15	Defendant receives notice of infringement from Rambus
2025-09-29	Asserted Patents assigned to Signal, LLP
2026-05-22	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 10,944,400 - "On-die termination control"

• Patent Identification: U.S. Patent No. 10,944,400, "On-die termination control," issued March 9, 2021.

The Invention Explained

• Problem Addressed: In high-speed memory systems, signal integrity is compromised by reflections on the data bus, especially in systems with multiple memory modules. A static termination impedance is often suboptimal, as the ideal termination value can change depending on whether a memory module is the target of a write operation or an idle bystander on the bus '902 Patent, col. 1:21-30
• The Patented Solution: The invention describes a memory controller that instructs a DRAM to use different on-die termination (ODT) values at different times. It commands the DRAM to store two distinct control values in two separate registers '400 Patent, claim 1 The first value specifies a "first termination" to be applied during a write operation, and the second value specifies a "second termination" to be applied after the write operation concludes, allowing for dynamic optimization of signal integrity ('402 Patent, abstract). This concept of using different termination values (e.g., "soft" vs. "hard") is detailed in the specification '902 Patent, col. 4:21-31
• Technical Importance: This "graduated termination" approach allows for finer control over impedance matching on the memory bus, enabling higher data rates and greater reliability in advanced DDR memory systems '902 Patent, col. 3:55-4:2

Key Claims at a Glance

• The complaint asserts at least independent Claim 1 Compl. ¶40
• Essential elements of Claim 1:
  • An integrated circuit device comprising a first signaling interface and control circuitry.
  • The signaling interface is to be coupled to a DRAM that has a first register and a second register.
  • The control circuitry transmits commands to the DRAM to store a first control value in the first register, specifying a first termination to be applied during a write-data reception interval.
  • The control circuitry transmits commands to the DRAM to store a second control value in the second register, specifying a second termination to be applied after the write-data reception interval.
• The complaint seeks relief for infringement of "one or more claims," which may suggest an intent to assert additional dependent claims Compl. ¶89(a)

U.S. Patent No. 8,947,962 - "On-die termination of address and command signals"

• Patent Identification: U.S. Patent No. 8,947,962, "On-die termination of address and command signals," issued February 3, 2015.

The Invention Explained

• Problem Addressed: Similar to the data bus, the address and command (RQ) bus in a high-speed memory system is also susceptible to signal reflections that can corrupt commands and addresses, leading to system errors. Terminating these lines is necessary, but a static "always-on" termination consumes significant power '439 Patent, col. 1:44-48
• The Patented Solution: The invention provides a memory controller that is "operable to selectively disable" the ODT circuitry within memory devices connected to the RQ bus '962 Patent, claim 1 This is achieved by the controller driving control signals on dedicated ODT control lines, allowing termination to be turned off when not needed, thereby saving power without compromising signal integrity during active command transmission '962 Patent, abstract The patent specification illustrates how an ODT circuit on a memory device can be enabled or disabled via a control pin '962 Patent, Fig. 1
• Technical Importance: Providing dynamic control over ODT for the address and command bus allows for a significant reduction in quiescent power consumption while maintaining the high-speed signaling performance required by modern memory standards '439 Patent, col. 3:45-50

Key Claims at a Glance

• The complaint asserts at least independent Claim 1 Compl. ¶50
• Essential elements of Claim 1:
  • A memory controller configured for connection to one or more memory devices via an address and control (RQ) bus.
  • Each memory device has ODT circuitry connected to a subset of the RQ bus signal lines.
  • The memory controller is operable to selectively disable the ODT circuitry in at least one memory device.
  • This disabling is accomplished by the controller driving control signals on a plurality of ODT control lines.
• The complaint seeks relief for infringement of "one or more claims," suggesting a possible intent to assert additional dependent claims Compl. ¶89(a)

U.S. Patent No. 9,092,352 - "Memory controller with write data error detection and remediation"

• Patent Identification: U.S. Patent No. 9,092,352, "Memory controller with write data error detection and remediation," issued July 28, 2015 Compl. ¶29
• Technology Synopsis: The patent addresses data corruption during high-speed memory write operations. The solution involves a memory controller that generates first error-detection information (e.g., a CRC) for a block of write data, receives corresponding error information back from the DRAM device, and performs a remedial action, such as retransmitting the data, if an error is detected Compl. Ex. 3, p. 14
• Asserted Claims: At least independent Claim 1 Compl. ¶60
• Accused Features: The accused products are alleged to infringe by incorporating memory controllers that perform write data error detection and remediation, consistent with JEDEC standards for DDR4 memory Compl. Ex. 3, pp. 7-15

U.S. Patent No. 10,056,902 - "On-die termination control"

• Patent Identification: U.S. Patent No. 10,056,902, "On-die termination control," issued August 21, 2018 Compl. ¶30
• Technology Synopsis: This patent, part of the same family as the '400 patent, describes controlling termination impedance on a data interface. The invention involves an integrated circuit device that sends commands to a DRAM to store a digital control value, which in turn dictates a specific termination impedance to be coupled to the data interface for a predetermined time after a write command, and then decoupled '902 Patent, claim 1
• Asserted Claims: At least independent Claim 1 Compl. ¶70
• Accused Features: The memory controllers within Ambarella's SoCs are accused of infringing by implementing dynamic on-die termination for their DDR memory interfaces Compl. Ex. 4, p. 4

U.S. Patent No. 10,115,439 - "On-die termination of address and command signals"

• Patent Identification: U.S. Patent No. 10,115,439, "On-die termination of address and command signals," issued October 30, 2018 Compl. ¶31
• Technology Synopsis: This patent, from the same family as the '962 patent, focuses on ODT for the command/address (CA) bus. The invention describes a memory controller that drives CA signals and a chip-select signal, and also stores register values in the memory device to represent and enable different ODT impedances for the CA signal inputs '439 Patent, claim 1
• Asserted Claims: At least independent Claim 1 Compl. ¶80
• Accused Features: The accused products' memory controllers are alleged to infringe by their ability to configure and apply ODT on the command and address bus, as required for operation with various JEDEC-compliant memory types Compl. Ex. 5, p. 3

III. The Accused Instrumentality

Product Identification

The "Accused Products" are a broad range of Ambarella's semiconductor products, including Systems-on-Chip (SoCs), microcontrollers (MCUs), and microprocessors (MPUs) that contain integrated memory controllers Compl. ¶¶14, 33 The complaint provides an extensive, non-limiting list of accused product families, such as the A12, CV22, H22, and N1 series, categorized by the DDR memory standards they support (e.g., DDR3, LPDDR4, LPDDR5/5X) Compl. ¶36

Functionality and Market Context

The accused products are high-performance SoCs targeted at markets including automotive, security cameras, and consumer electronics Compl. Ex. 2, p. 3 The core accused functionality is the integrated "Ambarella Memory System," which includes a "DDR Interface" for communicating with external high-speed DRAM Compl. Ex. 2, p. 4 The complaint provides a block diagram of the accused CV25S product, which shows the "Ambarella Memory System" and "DDR Interface" as central components for managing memory operations Compl. Ex. 2, p. 4 The complaint alleges these products are sold globally and form a significant part of Defendant's business Compl. ¶14

IV. Analysis of Infringement Allegations

The complaint references but does not attach claim-chart exhibits. The following summary is based on the infringement allegations and technical documents incorporated into the complaint. No probative visual evidence provided in complaint.

The complaint incorporates claim chart exhibits that were not publicly filed with the court. The following analysis is based on the narrative infringement theories and supporting technical documents presented in the exhibits that were filed.

10,944,400 Infringement Allegations

The complaint alleges infringement based on the accused products' compliance with JEDEC standards for DDR3, DDR4, and LPDDR5/5X memory (Compl. Ex. 1, pp. 10, 18, 23). For example, Exhibit 1 includes a block diagram of the accused A12AQ SoC, highlighting its "DDR3/DDR3L" memory interface Compl. Ex. 1, p. 5 The theory is that the Ambarella memory controller sends Mode Register Set (MRS) commands to the DRAM to store control values in registers like MR1 and MR2, which control different termination values (Rtt_WR and Rtt_Nom) for different operational states (Compl. Ex. 1, pp. 12, 17).

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
An integrated circuit device comprising: a first signaling interface to be coupled to a dynamic random access memory component (DRAM)...	The accused Ambarella SoCs are integrated circuit devices containing a memory controller with a signaling interface (e.g., "DDR Interface") for coupling to external DRAM.	¶40; Ex. 1, p. 4	'902 Patent, col. 4:21-25
...the DRAM having a first register to store a first control value and a second register to store a second control value...	The accused products are designed to operate with JEDEC-compliant DRAMs (e.g., DDR3, DDR4) which contain multiple Mode Registers (e.g., MR1, MR2, MR5) for storing control values.	¶40; Ex. 1, p. 12	'902 Patent, col. 4:5-15
...control circuitry to transmit... commands that instruct the DRAM to: store the first control value within the first register...specifying a first termination to be applied...during a write-data reception interval...	The control circuitry within the Ambarella memory controller allegedly transmits MRS commands to store a value (e.g., for Rtt_WR) in a first register (e.g., MR2) of the DRAM, which specifies a termination impedance applied during write operations.	¶40; Ex. 1, p. 36	'902 Patent, col. 4:26-31
...store the second control value within the second register...specifying a second termination that is to be applied...after the write-data reception interval transpires.	The control circuitry allegedly transmits MRS commands to store a different value (e.g., for Rtt_Nom or Rtt_Park) in a second register (e.g., MR1 or MR5) of the DRAM, which specifies a termination applied after the write interval.	¶40; Ex. 1, p. 46	'902 Patent, col. 3:63-4:2

• Identified Points of Contention:
  • Scope Questions: A central question will be whether the accused Ambarella SoC, which contains the memory controller, constitutes the "integrated circuit device" as claimed. A defendant may argue the claims read on the DRAM component, not the controller.
  • Technical Questions: What evidence does the complaint provide that Ambarella's "control circuitry" actually transmits the specific sequence of commands to "store the first control value" and then "store the second control value" in relation to a write interval? The infringement theory relies on the DRAM's capabilities as defined by JEDEC standards; the dispute will likely focus on whether the accused controller is proven to actively utilize this specific two-step dynamic termination scheme.

8,947,962 Infringement Allegations

The complaint's theory is that the accused products, by supporting standards like LPDDR4, include a memory controller that is "operable to selectively disable" ODT on the command/address bus Compl. Ex. 2, p. 17 Exhibit 2 includes a diagram from the JEDEC LPDDR4 standard showing that On-Die Termination for the Command/Address (CA) bus is controlled via Mode Register 11 (MR11), which includes a "disable" setting Compl. Ex. 2, p. 11

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
A memory controller configured to be connected to one or more memory devices via an address and control (RQ) bus...	The accused Ambarella SoCs are memory controllers with a "DDR Interface" that connects to external memory devices via an address and control bus.	¶50; Ex. 2, p. 3	'962 Patent, col. 1:24-27
...wherein: each of the memory devices have on-die termination (ODT) circuitry connected to a subset of signal lines of the address and control (RQ) bus...	The accused products are designed to connect to JEDEC-compliant memory devices (e.g., LPDDR4) that have ODT circuitry for the command/address (CA) bus.	¶50; Ex. 2, p. 9	'962 Patent, abstract
...and the memory controller is operable to selectively disable the ODT circuitry in at least one memory device...by driving control signals on a plurality of ODT control lines.	The Ambarella memory controller is allegedly operable to disable the ODT in the connected DRAM by writing a "disable" value to the appropriate Mode Register (e.g., MR11 in LPDDR4) via the CA bus, which acts as the ODT control lines.	¶50; Ex. 2, p. 17	'962 Patent, col. 2:37-43

• Identified Points of Contention:
  • Scope Questions: The case may turn on the construction of "operable to selectively disable." Plaintiff's position appears to be that capability is sufficient, while Defendant may argue that the claim requires proof that the controller is specifically configured to, and does, use this disabling feature in its normal operation.
  • Technical Questions: Does the command/address bus itself function as the "plurality of ODT control lines" for the purpose of disabling ODT, as the complaint's theory appears to require? Or does the claim envision separate, dedicated control lines distinct from the command/address bus?

V. Key Claim Terms for Construction

• Term: "control circuitry to transmit ... commands that instruct the DRAM to ... store the first control value ... and store the second control value" ('400 Patent, Claim 1)

  • Context and Importance: This term is the central active step of the claim. Its construction will determine the evidentiary burden on the plaintiff. Practitioners may focus on this term because the infringement allegation hinges on whether designing a controller to be compatible with a JEDEC-standard DRAM (which has these capabilities) is sufficient to meet the claim, or if proof is required that the controller itself specifically executes this two-part storage instruction as part of its routine operation.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification of the related '902 patent describes the invention in terms of a memory controller that "may assert the termination control signal" to cause the DRAM to act, suggesting a focus on the controller's capability to cause an effect '902 Patent, col. 3:25-28 This may support an interpretation where the ability to send standard MRS commands that result in the claimed storage is sufficient.
    • Evidence for a Narrower Interpretation: The claim requires instructing the DRAM to "store" a first value and then "store" a second value in relation to a write interval. A defendant may argue this implies a specific, ordered sequence of commands intended for this dynamic switching purpose, not just the general ability to write to mode registers. The abstract describes a process where a first impedance is applied "during reception of the write data followed by a second... after the write data has been received," which suggests a tightly-coupled temporal sequence that might require more than just generic capability '902 Patent, abstract

• Term: "operable to selectively disable" ('962 Patent, Claim 1)

  • Context and Importance: This term is critical to the scope of infringement. The plaintiff's case, as pleaded, appears to rely on the capability of Ambarella's controllers to disable ODT by virtue of their JEDEC compliance. The definition of "operable to" will determine whether this capability is enough to infringe.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent focuses on providing a controller that can work with memory devices having ODT. The abstract states the controller is "operable to selectively disable the ODT circuitry," which on its face suggests a capability '962 Patent, abstract This could support a reading where a device designed to be compatible with and capable of controlling a JEDEC-standard ODT feature is "operable to" perform the function.
    • Evidence for a Narrower Interpretation: The claim requires this disabling to occur "by driving control signals on a plurality of ODT control lines." A defendant might argue that "operable to" requires the controller to be configured to actually use this feature, not merely possess a latent capability. The specification's discussion of using a control pin (CAODT) to "actively enable and disable" termination might be used to argue that the patent contemplates active, intentional control, not just passive capability '962 Patent, col. 3:6-14

VI. Other Allegations

• Indirect Infringement: The complaint alleges inducement of infringement for all five patents. The factual basis is that Ambarella, with knowledge of the patents since at least November 15, 2022, has continued to provide its customers with the accused products along with "advertisements and instructive materials," "technical documentation," and support services that encourage and facilitate the infringing use of the products Compl. ¶¶42-43 Compl. ¶¶52-53
• Willful Infringement: The complaint alleges willful infringement for all five patents, seeking enhanced damages. The primary basis for this allegation is the pre-suit notice of infringement that Rambus (Plaintiff's predecessor) allegedly provided to Ambarella on November 15, 2022, which purportedly established "actual knowledge of the Asserted Patents" Compl. ¶¶10, 46, 56 The complaint alleges that Ambarella's continued infringement after this date has been deliberate and in conscious disregard of Plaintiff's patent rights Compl. ¶11

VII. Analyst's Conclusion: Key Questions for the Case

• A core issue will be one of capability versus action: can Signal prove infringement by showing Ambarella's controllers are merely capable of performing the claimed ODT control and error-remediation functions by virtue of their compliance with JEDEC standards, or must Signal provide evidence that the controllers actually execute the specific steps recited in the claims during their normal operation? The construction of claim terms like "operable to" and "control circuitry to transmit...commands that instruct" will be dispositive.
• A key evidentiary question will be one of proving internal functionality: what level of evidence will be required to demonstrate the inner workings of Ambarella's proprietary "Ambarella Memory System"? The case as pleaded relies heavily on public product briefs and industry standards, and its progression will likely depend on what discovery reveals about the actual hardware and software implementation of the accused memory controllers.
• A third pivotal question will be one of claim scope: can the term "ODT control lines" as used in the '962 patent be interpreted to read on a general-purpose command/address bus that is used to write to a mode register, or does the patent require physically or functionally distinct lines for the purpose of controlling ODT?