DCT

1:26-cv-13729

JMG Ventures LLC v. Microsoft Corp

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:26-cv-13729, D. Mass., 08/13/2026
  • Venue Allegations: Plaintiff alleges venue is proper in the District of Massachusetts because Defendant Microsoft maintains regular and established places of business within the district, including its New England Research & Development (NERD) Center and a Sales, Marketing and Services Group (SMSG) office. The complaint further alleges that Microsoft transacts business and develops, markets, and sells the Accused Products within the district. The complaint asserts federal subject-matter jurisdiction under 28 U.S.C. §§ 1331 and 1338(a) for claims arising under the patent laws, 35 U.S.C. § 271, and pleads that venue is proper under 28 U.S.C. §§ 1391(b) and (c) and § 1400(b).
  • Core Dispute: Plaintiff alleges that Defendant’s Xbox Series S and Xbox Series X game consoles, which utilize "Velocity Architecture," infringe two patents related to modular computer architectures designed to improve performance by reorganizing communication pathways between processing components and storage.
  • Technical Context: The technology pertains to high-performance computer system architecture, a field where minimizing data access latency is critical, particularly for demanding applications like modern video gaming.
  • Key Procedural History: The complaint pleads that the Patents-in-Suit were assigned by the inventor Glickman to JMG, with the assignment recorded with the USPTO on May 14, 2026, conveying the right to sue for infringement and collect damages and establishing JMG's standing. The complaint also demands a trial by jury under Rule 38. The complaint alleges that the inventor and Microsoft engaged in licensing discussions in "early 2019," during which Microsoft was allegedly provided with a copy of a patent related to the Patents-in-Suit. These discussions, which reportedly did not result in an agreement, are cited as the basis for Plaintiff's willful infringement allegations.

Case Timeline

Date Event
2013-05-01 Earliest Priority Date for '464 and '519 Patents
2016-10-18 U.S. Patent No. 9,471,519 Issues
Early 2019 Alleged licensing discussions begin between inventor and Microsoft
2020-11 Accused Xbox Series S/X Consoles First Released
2023-10-03 U.S. Patent No. 11,775,464 Issues
2026-05-14 Glickman-to-JMG Assignment of Patents-in-Suit Recorded with USPTO
2026-08-13 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 11,775,464

  • Patent Identification: U.S. Patent No. 11,775,464 (“the ’464 Patent”), titled “Computer System and a Computer Device,” issued on October 3, 2023 Compl. ¶11

The Invention Explained

  • Problem Addressed: The patent describes conventional computer architectures as suffering from performance bottlenecks, particularly where mechanical hard drives, and even faster solid-state drives (SSDs), are limited by the communication pathways connecting them to the CPU and memory (Compl. ¶¶15-16; ’464 Patent, col. 1:55-2:5). Centralized processing architectures also create limitations by over-relying on a main CPU for data management tasks Compl. ¶18 ’464 Patent, col. 2:42-50
  • The Patented Solution: The invention proposes a modular computer architecture built around "Sibling boards" Compl. ¶19 ’464 Patent, abstract These are self-contained computing modules, each with its own CPU and memory, that communicate over a common bus '464 Patent, col. 2:21-34 This design segregates high-speed components from slower input/output (I/O) peripherals, which are handled by a separate "hub board" '464 Patent, Fig. 7 This modularity allows for flexible system configurations, such as arranging boards in series or parallel to optimize for tasks like data prefetching and distributed processing '464 Patent, col. 6:51-60
  • Technical Importance: This architecture aimed to provide a more flexible and scalable approach to system design, allowing performance to be tailored to specific applications by overcoming the rigid structure of traditional motherboards Compl. ¶19 ’464 Patent, col. 3:53-4:7

Key Claims at a Glance

  • The complaint asserts independent claims 1 and 7 Compl. ¶67
  • Independent Claim 1 recites a computer gaming system with a bus, a hub portion with an I/O controller, and a main board with one or more “component units.” Key elements include:
    • Each component unit is a “computerized node” with a CPU and memory controller.
    • An embedded application compute kernel is used to pre-fetch data.
    • The controller utilizes one or more component units “coupled in series” for staging prefetching operations.
    • Each component unit can host an operating system on a dedicated physical resource.
  • Independent Claim 7 is nearly identical to Claim 1 but requires the controller to utilize one or more component units “coupled in parallel” for staging prefetching operations.
  • The complaint expressly reserves the right to assert additional claims Compl. ¶69

U.S. Patent No. 9,471,519

  • Patent Identification: U.S. Patent No. 9,471,519 (“the ’519 Patent”), titled “Computer System and a Computer Device,” issued on October 18, 2016 Compl. ¶11

The Invention Explained

  • Problem Addressed: The '519 Patent, which shares a specification with the '464 Patent, identifies the same problem of performance bottlenecks in traditional computer architectures caused by slow disk access and the limitations of centralized processing Compl. ¶15 '519 Patent, col. 1:50-60
  • The Patented Solution: The complaint characterizes the invention as a "multi-node computer architecture implemented within an IC," where multiple configurable processing units share a common bus and I/O hub Compl. ¶75 '519 Patent, claim 1 '519 Patent, claim 9 These units can communicate with one another and operate together in series or parallel as a disk controller to perform "staged data prefetching," allowing for a flexible and high-performance system-on-a-chip (SoC) design '519 Patent, abstract '519 Patent, col. 2:9-34
  • Technical Importance: The patent provides a blueprint for an integrated, modular SoC architecture that aims to overcome the I/O and processing limitations inherent in conventional, less integrated designs Compl. ¶19 '519 Patent, col. 4:15-24

Key Claims at a Glance

  • The complaint asserts independent claims 1 and 9 Compl. ¶77
  • Independent Claim 1 recites a computer system implemented in an integrated circuit (IC) with a common bus, a hub portion, and a plurality of “IC units.” Key elements include:
    • Two or more IC units are “coupled in series.”
    • Each IC unit is configurable to operate as a master node, a slave node, or a portion of a disk controller.
    • The disk controller uses an embedded kernel to pre-fetch data for "staging prefetching operations."
    • Each IC unit is capable of hosting an operating system.
  • Independent Claim 9 is similar to Claim 1 but requires two or more IC units to be “coupled in parallel.”
  • The complaint expressly reserves the right to assert direct infringement of additional claims Compl. ¶79

III. The Accused Instrumentality

  • Product Identification: The accused instrumentalities are Microsoft’s Xbox Series S and Xbox Series X game consoles (the “Accused Products”) Compl. ¶25
  • Functionality and Market Context:
    • The complaint alleges that the Accused Products implement a novel “Velocity Architecture” to achieve a significant performance leap over prior console generations Compl. ¶33 Compl. ¶36 This architecture comprises a custom NVMe SSD, a “DirectStorage” API, dedicated decompression hardware, and “Sampler Feedback Streaming” Compl. ¶36
    • The core of the system is a custom AMD System-on-a-Chip (SoC) that integrates Zen 2 CPU cores, RDNA 2 GPU Compute Units (CUs), a memory subsystem, and an I/O Hub that communicates with peripherals Compl. ¶42 An "Xbox Series X | SOC Block Diagram" included in the complaint illustrates these distinct functional blocks and their interconnections Compl. p. 16
    • The complaint alleges this architecture creates a data "pipeline" where the CPU initiates asset requests via DirectStorage, the NVMe SSD retrieves the data, and dedicated hardware decompresses it directly into shared memory for use by the GPU, thereby minimizing CPU overhead and latency Compl. ¶¶56-57 This process is depicted in a "Flow of GPU assets" diagram Compl. p. 23
    • The console electronics are described as having a "split-motherboard" layout, with the electronics distributed across separate circuit-board assemblies; the custom SoC remains the principal compute device, and a "southbridge-type I/O controller" functions as the communications hub to lower-speed peripheral devices Compl. ¶58

IV. Analysis of Infringement Allegations

U.S. Patent No. 11,775,464 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a bus The internal system interconnect fabric of the custom SoC and the PCIe bus extension that enables communication among components Compl. ¶68 ¶68 col. 2:21-34
a hub portion coupled to the bus, the hub portion comprising an input/output controller for communicating with one or more periphery component devices An on-SoC I/O Hub, described as distinct from the "southbridge-type" I/O controller of the peripheral subsystem, that manages communications with peripheral devices like USB and Ethernet Compl. ¶42 Compl. ¶58 Compl. ¶68 ¶58; ¶68 col. 2:42-50
a main board comprising one or more component units, each component unit being in direct communication with the bus and one or more of the other component units residing on the main board The custom SoC, described as part of a "motherboard architecture," containing multiple components like Zen 2 CPU cores and RDNA 2 GPU CUs that communicate via the system interconnect Compl. ¶68 ¶68 col. 3:53-4:7
each component unit residing on the main board is configurable to operate as a computerized node that comprises a controller and memory, wherein the controller comprises a central processing unit (CPU) and a memory controller The Zen 2 CPU cores, RDNA 2 GPU Compute Units, and the NVMe SSD/controller are alleged to be "component units," each with its own processing, memory, and memory-control functionality Compl. ¶47 Compl. ¶51 Compl. ¶68 ¶47; ¶51; ¶68 col. 2:21-34
wherein the controller comprises an embedded application compute kernel to pre-fetch data, wherein the controller utilizes one or more of the component units coupled in series for staging prefetching operations The DirectStorage API, which coordinates a "pipeline" in which the SSD and decompression hardware are alleged to operate "in parallel as a pipeline" to retrieve, decompress, and stage game assets for CPU/GPU use Compl. ¶56 Compl. ¶57 Compl. ¶68 ¶56; ¶57; ¶68 col. 6:39-60
each component unit is capable of hosting an operating system on a dedicated physical resource The complaint alleges each component unit (e.g., CPU cores, GPU CUs) comprises processing, memory, and memory-control functionality coordinated by DirectStorage; it does not expressly allege that each unit hosts an operating system on a dedicated physical resource Compl. ¶68 ¶68 col. 3:53-4:7

U.S. Patent No. 9,471,519 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A computer system comprising: an integrated circuit (IC) comprising: a common bus; a hub portion...including an input/output controller configured to communicate with a plurality of periphery devices; and a plurality of IC units, each IC unit being in communication with the common bus and two or more of the IC units being coupled in series The Accused Products comprise a custom SoC (the "IC") that integrates multiple processing units ("IC units") such as Zen 2 CPU cores, RDNA 2 GPU CUs, and memory/I/O circuitry, all communicating via the SoC's internal interconnect ("common bus") and with an I/O controller ("hub portion") Compl. ¶78 The complaint alleges these IC units are "operable in parallel" as a pipeline and does not expressly allege a "coupled in series" operation Compl. ¶78 ¶78 col. 2:9-34
each IC unit being configurable to operate as at least one of a master node, a slave node, and a portion of a disk controller including an embedded application kernel to pre-fetch data from a storage array, when configured as the portion of the disk controller, the portion of the disk controller utilizes two or more of the IC units...for staging prefetching operations The DirectStorage/Velocity Architecture storage pipeline accommodates prefetching where game software submits requests, the NVMe SSD retrieves assets, and dedicated hardware performs decompression and stages the data for use by the CPU and GPU Compl. ¶78 ¶78 col. 4:15-24

Identified Points of Contention

  • Scope Questions: A primary question will be whether the term "component unit" (or "IC unit"), described in the specification with reference to modular "Sibling boards," can be construed to cover the integrated-yet-distinct functional blocks (CPU cores, GPU CUs, I/O Hub) of Microsoft's custom SoC. The defense may argue these are standard SoC components, not the physically and operationally distinct modules envisioned by the patents.
  • Technical Questions: Both patents have claims requiring components "coupled in series" and "coupled in parallel" for prefetching. The complaint alleges the Accused Products' single "Velocity Architecture" infringes both types of claims, describing it as a "pipeline" where components operate "in parallel as a pipeline" Compl. ¶56 This raises the question of whether a single architecture can simultaneously meet the definitions of both "series" and "parallel" coupling as claimed, or whether the two claimed configurations describe distinct technical operations.

V. Key Claim Terms for Construction

  • The Term: "component unit" (’464 Patent) / "IC unit" (’519 Patent)

    • Context and Importance: The definition of this term is central to infringement. The dispute will likely focus on whether it requires the physically separate, pluggable "Sibling boards" described as a primary embodiment in the specification, or if it can functionally encompass distinct processing blocks integrated within a single SoC.
    • Intrinsic Evidence for a Broader Interpretation: The claims themselves suggest a functional definition by providing examples of what a "component unit" may be, including a GPU, a network component, or an SSD '464 Patent, claim 1 This language may support an interpretation that covers any distinct functional processing block.
    • Intrinsic Evidence for a Narrower Interpretation: The specification repeatedly emphasizes the modularity of "Sibling boards" that can be physically arranged in series or parallel and plugged into a common bus, each capable of hosting its own operating system '464 Patent, col. 3:53-4:7 '464 Patent, abstract This could support a narrower construction requiring a degree of physical and operational independence not present in a fully integrated SoC.

  • The Term: "coupled in series for staging prefetching operations"

    • Context and Importance: This limitation defines the core function of Claim 1 in both patents. The interpretation of "coupled in series" will determine whether the alleged data pipeline in the Accused Products infringes.
    • Intrinsic Evidence for a Broader Interpretation: The patent specification describes "chaining Sibling boards as disk controllers one after the other" for multi-stage prefetching '464 Patent, col. 6:39-42 This language could support a functional interpretation where "series" means a sequential data-flow pipeline, as alleged by the plaintiff Compl. ¶56
    • Intrinsic Evidence for a Narrower Interpretation: The figures depicting series configurations (e.g., ’464 Patent, Fig. 4) show a literal, physical chain of distinct boards. This could be used to argue that "coupled in series" requires a specific physical or electrical connection topology between discrete units, rather than just a logical sequence of operations within an integrated circuit.

VI. Other Allegations

  • Indirect Infringement: The complaint pleads only direct infringement and does not allege any theory of induced or contributory infringement; it expressly reserves the right to assert direct infringement of additional claims of the '519 Patent Compl. ¶79
  • Relief Requested: The complaint's prayer for relief seeks a judgment of direct infringement (literally or under the doctrine of equivalents), damages adequate to compensate for the infringement, treble or enhanced damages under 35 U.S.C. § 284, pre- and post-judgment interest, a finding that the case is exceptional and an award of attorney's fees under 35 U.S.C. § 285, and a permanent injunction or, in the alternative, a post-judgment royalty Compl. p. 31
  • Willful Infringement: The complaint alleges willful infringement of both patents Compl. ¶71 Compl. ¶81 The basis for this allegation is purported pre-suit knowledge stemming from licensing discussions that allegedly began in "early 2019," during which Microsoft was provided with a related Glickman patent sharing an identical specification to the patents-in-suit Compl. ¶60 Compl. ¶81 For the '519 Patent, the complaint alleges that all sales of the Accused Products, which launched in November 2020, were made after Microsoft obtained actual knowledge of that patent Compl. ¶81 For the later-issued '464 Patent, the complaint instead pleads that Microsoft has had actual knowledge or constructive notice only since the '464 Patent's 2023 issuance—after the November 2020 launch Compl. ¶71

VII. Analyst’s Conclusion: Key Questions for the Case

  • Definitional Scope: A core issue will be one of claim construction: can the patents' concept of modular, physically distinct "Sibling boards" be interpreted to cover the highly integrated, yet functionally separate, processing blocks within Microsoft’s custom System-on-a-Chip? This question may turn on whether the court adopts a narrow, structural definition or a broader, functional one for the term "component unit."
  • Architectural Equivalence: A central evidentiary question will be whether Microsoft's "Velocity Architecture" pipeline constitutes the specific "coupled in series" and/or "coupled in parallel" configurations required by the asserted claims for prefetching. The case may turn on whether the plaintiff can prove that a single accused architecture meets the technical requirements of what appear to be mutually exclusive claim limitations.
  • Knowledge and Intent: The willfulness claim will depend on the factual evidence surrounding the alleged "early 2019" licensing discussions. Key questions for the court will be what was disclosed, whether knowledge of a related patent constitutes knowledge of the subsequently asserted patents, and whether Microsoft acted with the specific knowledge or reckless blindness alleged in the complaint.