JMG Ventures LLC v. Microsoft Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: JMG Ventures LLC (Massachusetts)
  • Defendant: Microsoft Corp (Washington)
  • Plaintiff's Counsel: PEARL COHEN LLP
• Case Identification: 1:26-cv-13729, D. Mass., 08/13/2026
• Venue Allegations: Venue is asserted based on Defendant Microsoft maintaining regular and established places of business within the District of Massachusetts, including its New England Research & Development (NERD) Center and its Sales, Marketing and Services Group.
• Core Dispute: Plaintiff alleges that Defendant's Xbox Series S and Xbox Series X game consoles, which utilize a "Velocity Architecture," infringe two patents related to a modular computer architecture designed to circumvent performance bottlenecks.
• Technical Context: The technology domain is high-performance computer architecture, specifically methods of arranging processors, memory, and storage to reduce latency and improve data throughput in computationally demanding applications like video gaming.
• Key Procedural History: The complaint alleges that Microsoft was provided with a copy of a related patent with an identical specification in early 2019 and that licensing discussions occurred but did not result in an agreement, a fact pattern asserted in support of willful infringement.

Case Timeline

Date	Event
2013-05-01	Priority Date for '519 and '464 Patents
2016-10-18	U.S. Patent No. 9,471,519 Issued
2019-01-01	Approximate start of alleged licensing discussions
2020-11-01	Accused Products (Xbox Series S/X) First Released
2023-10-03	U.S. Patent No. 11,775,464 Issued
2026-08-13	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 11,775,464 - "Computer System and a Computer Device"

• Patent Identification: U.S. Patent No. 11,775,464 ("'464 Patent"), issued October 3, 2023.

The Invention Explained

• Problem Addressed: The patent's background describes a performance bottleneck in conventional computer architectures where, even with the advent of fast solid-state drives (SSDs), the communication medium and centralized architecture limit overall system speed Compl. ¶16 '464 Patent, col. 1:55-2:5 Disk access was traditionally a greater bottleneck than network switches, but the speed of SSDs shifted this problem '464 Patent, col. 1:60-62
• The Patented Solution: The invention proposes a modular computer architecture using "Sibling boards" '464 Patent, abstract These are self-contained computing modules (with CPU, memory, etc.) that can be flexibly configured in series or parallel on a common bus to optimize performance for specific tasks like data prefetching '464 Patent, col. 3:53-4:7 '464 Patent, Figs. 2-4 A separate "peripheral hub board" handles communication with slower external devices, thereby separating high-speed and low-speed components to improve efficiency '464 Patent, col. 2:16-24
• Technical Importance: This architectural approach was designed to overcome the limitations of rigid motherboard designs and fully leverage the speed of modern components like SSDs in distributed computing environments Compl. ¶15

Key Claims at a Glance

• The complaint asserts independent claims 1 and 7 Compl. ¶¶65-66
• Essential elements of independent claim 1 include:
  • A bus.
  • A hub portion with an input/output controller for periphery devices.
  • A main board with one or more "component units" in direct communication with the bus.
  • Each "component unit" is configurable as a "computerized node" with a controller (CPU, memory controller) and memory.
  • The "component units" can be a CPU/SOC, GPU, SSD, or application component.
  • The controller has an embedded application compute kernel to pre-fetch data.
  • The controller utilizes one or more "component units" that are "coupled in series" for staging prefetching operations.
  • Each "component unit" is capable of hosting its own operating system on a dedicated physical resource.
• The complaint notes that claim 7 is similar to claim 1 but recites "component units" that are "coupled in parallel" (Compl. ¶66).
• The complaint reserves the right to assert additional claims Compl. ¶69

U.S. Patent No. 9,471,519 - "Computer System and a Computer Device"

• Patent Identification: U.S. Patent No. 9,471,519 ("'519 Patent"), issued October 18, 2016.

The Invention Explained

• Problem Addressed: The '519 Patent shares an identical specification with the '464 Patent and addresses the same problem of performance bottlenecks in conventional computer architectures Compl. ¶60 '519 Patent, col. 1:55-2:5
• The Patented Solution: The solution is the same modular "Sibling board" architecture described for the '464 Patent, which allows for flexible series or parallel configurations of computing modules on a common bus to improve data processing and prefetching '519 Patent, abstract '519 Patent, col. 3:53-4:7
• Technical Importance: This architecture aimed to create a more flexible, powerful, and cost-effective alternative to rigid, centralized computer designs Compl. ¶19

Key Claims at a Glance

• The complaint asserts independent claims 1 and 9 Compl. ¶¶75-76
• Essential elements of independent claim 1 include:
  • An integrated circuit (IC) comprising a common bus, a hub portion, and a plurality of "IC units".
  • The hub portion includes an input/output controller.
  • Two or more "IC units" are "coupled in series".
  • Each "IC unit" is configurable as a master/slave node or as part of a disk controller with a pre-fetch kernel.
  • The disk controller portion utilizes two or more "IC units" "coupled in series" for staging prefetching.
  • Each "IC unit" is capable of hosting an operating system.
• The complaint notes that claim 9 is similar to claim 1 but recites "IC units" that are "coupled in parallel" (Compl. ¶76).
• The complaint reserves the right to assert additional claims Compl. ¶79

III. The Accused Instrumentality

Product Identification

• The accused products are Microsoft's Xbox Series S and Xbox Series X game consoles Compl. ¶25

Functionality and Market Context

• The core of the accused functionality is the "Velocity Architecture," which the complaint describes as a storage and asset-streaming system that represents a "fundamentally different relationship among storage, memory, CPU and GPU" compared to prior console generations Compl. ¶36 Compl. ¶41
• This architecture is built around a custom AMD System-on-a-Chip (SOC) that integrates Zen 2 CPU cores and RDNA 2 GPU Compute Units (CUs) Compl. ¶42 A diagram in the complaint shows the SOC block diagram, including the CPU, GPU, Media Hub, and I/O Hub Compl. ¶42 The architecture uses a custom NVMe SSD for storage, which communicates with the SOC via a high-bandwidth PCIe bus Compl. ¶50 Compl. ¶55
• A key feature is the "DirectStorage" API, which allows games to efficiently manage I/O requests between the GPU and SSD, substantially reducing CPU overhead Compl. ¶38 Compl. ¶45 The complaint includes a diagram illustrating the flow of game assets from the NVMe SSD, through a system memory copy, to the GPU for decompression, a process that avoids routing data through the CPU for processing Compl. ¶¶56-57

IV. Analysis of Infringement Allegations

'464 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a hub portion coupled to the bus, the hub portion comprising an input/output controller...	The Xbox SOC contains a "southbridge-type I/O controller" that functions as a communications hub for peripheral devices like USB, Ethernet, and storage Compl. ¶58	¶58	col. 2:16-24
a main board comprising one or more component units...each component unit being in direct communication with the bus	The custom SOC is alleged to be the main board, and its integrated functional blocks-the Zen 2 CPU cores, RDNA 2 GPU CUs, and the SSD controller-are alleged to be the "component units" that communicate via the SOC's internal interconnect fabric (the "bus") Compl. ¶68	¶68	col. 14:38-42
each component unit is configured to operate at least as a...graphical processing unit (GPU)...a solid state drive (SSD)	The Accused Products contain RDNA 2 GPU Compute Units and a custom NVMe SSD, which are alleged to be "component units" Compl. ¶46 Compl. ¶50	¶46; ¶50	col. 14:1-5
the controller utilizes one or more of the component units coupled in series for staging prefetching operations	The "Velocity Architecture" creates a hardware pipeline where the NVMe SSD, dedicated decompression hardware, and GPU operate sequentially to retrieve, decompress, and deliver game assets for use, which is alleged to be a "series" coupling Compl. ¶53 Compl. ¶57	¶53; ¶57	col. 6:51-54

'519 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
an integrated circuit (IC) comprising: a common bus; a hub portion...and a plurality of IC units	The custom AMD SOC in the Accused Products is alleged to be the claimed "integrated circuit." The SOC's internal interconnect fabric is the "common bus," the I/O hub is the "hub portion," and the functional blocks (CPU cores, GPU CUs) are the "IC units" Compl. ¶78	¶78	col. 13:50-58
each IC unit being in communication with the common bus and two or more of the IC units being coupled in series	The Zen 2 CPU cores and RDNA 2 GPU CUs communicate via the SOC's internal interconnect. The DirectStorage pipeline is alleged to create a "series" coupling between the SSD controller, decompression hardware, and GPU Compl. ¶78	¶78	col. 13:58-61
the portion of the disk controller utilizes two or more of the IC units...coupled in series for staging prefetching operations	The DirectStorage system, which coordinates the retrieval of assets from the NVMe SSD and their decompression, allegedly uses the SSD controller and decompression hardware (as "IC units") in a series pipeline to perform prefetching Compl. ¶78 A diagram provided in the complaint shows the GPU diagram for the Xbox Series X, detailing the multiple Compute Units (CUs) that are alleged to be IC units Compl. ¶46	¶78	col. 14:5-9
wherein each IC unit...is capable of...hosting an operating system	The complaint alleges that the CPU cores, GPU CUs, and SSD controller structures each contain processing and memory-control functionality, implicitly suggesting they are capable of hosting an operating system or its equivalent functions Compl. ¶68	¶68	col. 14:14-17

• Identified Points of Contention:
  • Scope Questions: A central question for both patents is whether the terms "component unit" and "IC unit", described in the specifications as physically separate, modular "Sibling boards" that plug into a common bus, can be construed to read on the highly integrated, non-modular functional blocks (e.g., CPU cores, GPU compute units) within a single System-on-a-Chip. The complaint's visual evidence, such as the SOC diagram, highlights this integrated nature Compl. ¶42
  • Technical Questions: The complaint asserts infringement of claims requiring components to be "coupled in series" and, in the alternative, "coupled in parallel" for prefetching. A point of contention may be whether the accused "Velocity Architecture" data pipeline technically meets the definition of either configuration as contemplated by the patents, which depict distinct physical arrangements for series and parallel operations.

V. Key Claim Terms for Construction

• The Term: "component unit" ('464 patent) / "IC unit" ('519 patent)

  • Context and Importance: The definition of these terms is fundamental to the infringement analysis. The plaintiff's theory requires these terms to cover functional blocks within a single SOC, while the patent specification repeatedly illustrates them as physically separate, modular boards. Practitioners may focus on this term because its construction could determine whether the accused highly integrated SOC architecture falls within the scope of an invention described as a system of physically modular boards.
  • Intrinsic Evidence for a Broader Interpretation: The claims themselves list examples of what a "component unit" can be, including a "CPU system-on-a-chip (CPU/SOC), a graphical processing unit (GPU), [and] a solid state drive (SSD)" '464 Patent, col. 14:1-5 This list may support an interpretation that the term refers to functional roles rather than physical form factor.
  • Intrinsic Evidence for a Narrower Interpretation: The detailed description and figures consistently depict the invention as a system of distinct "Sibling boards" that "physically plugs into a common bus" '464 Patent, col. 2:25-27 '464 Patent, Figs. 1-4 The abstract of the '519 Patent describes a "plurality of Sibling boards" and a "hub board," reinforcing the physically modular nature of the described embodiments.

• The Term: "coupled in series" / "coupled in parallel"

  • Context and Importance: These terms differentiate the asserted independent claims in both patents. Their construction will be critical for determining whether the data flow in the accused "Velocity Architecture" performs the claimed "staging prefetching operations" in the manner required.
  • Intrinsic Evidence for Interpretation: The patent specification provides distinct diagrams for each configuration. Figure 4 shows "Sibling boards" chained together as a "Series-Series" arrangement for prefetching '464 Patent, Fig. 4 '464 Patent, col. 6:30-40 Figure 2 shows a "Parallel" arrangement where boards connect to the same common bus '464 Patent, Fig. 2 '464 Patent, col. 6:7-15 Parties may dispute whether the "coupling" must be a physical arrangement as shown in the figures or can refer to a logical data-flow relationship.

VI. Other Allegations

• Willful Infringement: The complaint alleges willful infringement for both patents. The basis for this allegation is Microsoft's purported actual knowledge of the inventor's technology and patent family, allegedly stemming from correspondence and licensing discussions that began in early 2019, prior to the release of the Accused Products (Compl. ¶60; Compl. ¶61). For the '464 Patent, willfulness is alleged from its issue date, and for the '519 Patent, from at least early 2019 Compl. ¶71 Compl. ¶81

VII. Analyst's Conclusion: Key Questions for the Case

1. A core issue will be one of definitional scope: can the terms "component unit" and "IC unit", which the patent specifications describe in the context of physically distinct and modular "Sibling boards," be construed broadly enough to read on the integrated functional blocks (e.g., CPU cores, GPU compute units) residing within the accused consoles' single, monolithic System-on-a-Chip?
2. A second central question will be one of operational equivalence: does the data pipeline in the accused "Velocity Architecture"-where the CPU initiates I/O requests that are then handled by a sequence of dedicated hardware (SSD, decompressor) to deliver data to the GPU-constitute the specific "coupling in series" or "coupling in parallel" of "component units" for "staging prefetching operations" as required by the claims and described in the patent's embodiments?
3. An evidentiary question will be one of knowledge and intent: what was the specific content of the alleged 2019 communications between the parties, and does it establish that Microsoft had pre-suit knowledge of the specific patented technology with a specific intent to infringe, sufficient to support a finding of willfulness?