Advanced Memory Tech LLC v. Micron Technology Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Advanced Memory Technologies, LLC (Texas)
  • Defendant: Micron Technology, Inc. (Delaware)
  • Plaintiff's Counsel: Susman Godfrey L.L.P.
• Case Identification: 1:25-cv-01036, W.D. Tex., 11/04/2025
• Venue Allegations: Venue is alleged based on Defendant Micron Technology, Inc.'s regular and established places of business within the Western District of Texas, including a research and development facility in Austin known as the Micron Storage Solutions Center. The complaint further alleges that the Court has specific personal jurisdiction over Defendant under principles of due process and the Texas Long Arm Statute based on Defendant's minimum contacts with the forum.
• Core Dispute: Plaintiff alleges that Defendant's NAND flash and DRAM semiconductor memory modules infringe five U.S. patents related to the design of booster circuits and internal voltage generation circuitry.
• Technical Context: The technology at issue involves fundamental circuit designs for managing on-chip voltages in semiconductor memory, a critical function for performance and power efficiency in a vast array of modern consumer and enterprise electronic devices.
• Key Procedural History: The complaint is a First Amended Complaint, superseding an initial complaint filed on June 30, 2025. Plaintiff alleges that Defendant had pre-suit knowledge of two asserted patents ('018 and '557) as early as 2011, stemming from a patent prosecution where Defendant was the assignee and the '557 patent's published application (Pub. No. 2008-0169864) was cited as prior art. The complaint further alleges that Plaintiff owns each Asserted Patent by assignment, including the sole and exclusive right to sue for infringement, and demands a jury trial on all issues so triable.

Case Timeline

Date	Event
2007-01-17	Priority Date for U.S. Patent Nos. 7,920,018 and 7,777,557
2008-07-09	Priority Date for U.S. Patent No. 7,969,231
2009-12-03	Priority Date for U.S. Patent No. 8,519,778
2010-03-04	'557 Patent application cited as prior art in prosecution of patent application assigned to Micron
2010-03-10	Priority Date for U.S. Patent No. 8,593,888
2010-08-17	U.S. Patent No. 7,777,557 Issued
2011-04-05	U.S. Patent No. 7,920,018 Issued
2011-06-28	U.S. Patent No. 7,969,231 Issued
2011-09-30	Alleged date of Micron's knowledge of the '018 and '557 Patents
2013-08-27	U.S. Patent No. 8,519,778 Issued
2013-11-26	U.S. Patent No. 8,593,888 Issued
2016	Micron opened the Micron Storage Solutions Center in Austin
2025-06-30	Initial Complaint Filed
2025-11-04	First Amended Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,920,018 - "Booster Circuit"

• Patent Identification: U.S. Patent No. 7,920,018, "Booster Circuit," issued April 5, 2011 Compl. ¶15
• The Invention Explained:
  • Problem Addressed: Conventional booster circuits can suffer from reduced efficiency and increased layout area due to parasitic capacitance formed by well structures within transistors, which are wastefully charged and discharged during operation '557 Patent, col. 2:12-29
  • The Patented Solution: The invention proposes a booster circuit with two rows of boosting cells and an analog comparison circuit. This comparison circuit intelligently controls the potential of a well region within the transistors by selecting the lower or higher of the input potentials from cells in the two rows '018 Patent, col. 3:7-16 By fixing the well potential based on the stage's input, the invention aims to suppress the wasteful charging/discharging of parasitic capacitance and improve boost efficiency '018 Patent, col. 4:63-col. 5:2
  • Technical Importance: This design allows for more power-efficient and area-efficient on-chip voltage generation, a key requirement for high-performance, low-power semiconductor memory devices like flash memory '557 Patent, col. 1:8-15
• Key Claims at a Glance:
  • The complaint asserts at least Claim 1 Compl. ¶41
  • Independent Claim 1 of the '018 Patent recites:
    • a first boosting cell row including N stages (N≥1) of the boosting cells;
    • a second boosting cell row including M stages (M≥1) of boosting cells;
    • at least one analog comparison circuit for outputting a well bias potential generated by an input potential of the boosting cell on the i-th stage of the first row and an input potential of the boosting cell on the i-th stage of the second row;
    • wherein each boosting cell includes a first-conductivity type first well region, a second-conductivity type second well region, and a switching element;
    • the switching element is configured to transfer charges; and
    • the well bias potential from the analog comparison circuit is applied to the first well region of the switching element in the boosting cells.
  • The complaint reserves the right to assert additional claims Compl. ¶41

U.S. Patent No. 7,969,231 - "Internal Voltage Generating Circuit"

• Patent Identification: U.S. Patent No. 7,969,231, "Internal Voltage Generating Circuit," issued June 28, 2011 Compl. ¶20
• The Invention Explained:
  • Problem Addressed: In conventional voltage generating circuits, there is a trade-off between the speed of initial voltage ramp-up (setup time) and power efficiency during steady-state operation. Using large boost capacitances to speed up setup time can lead to poor use efficiency and a larger circuit area '231 Patent, col. 4:1-12
  • The Patented Solution: The invention uses two charge pump circuits in series. Crucially, it incorporates a frequency dividing circuit and a buffer circuit that can select between a high-frequency clock signal and a lower-frequency, divided clock signal to drive the second charge pump '231 Patent, col. 4:25-34 This allows the circuit to use a fast clock for rapid initial voltage setup and then switch to a slower, more power-efficient clock for voltage maintenance '231 Patent, col. 7:40-49
  • Technical Importance: This dual-frequency approach provides a method to achieve both fast performance at startup and low power consumption during normal operation, optimizing the overall performance of the voltage generating circuit.
• Key Claims at a Glance:
  • The complaint asserts at least Claims 3 and 6 Compl. ¶63
  • Independent Claim 3 of the '231 Patent recites:
    • a first charge pump circuit configured to generate a second voltage from a first voltage;
    • a second charge pump circuit configured to generate a third voltage from the second voltage;
    • a frequency dividing circuit configured to divide a first clock signal to generate a second clock signal; and
    • a buffer circuit configured to select the first clock signal or the second clock signal and generate a third clock signal, which is supplied to the second charge pump circuit.
  • Independent Claim 6 of the '231 Patent recites:
    • a first charge pump circuit configured to generate a second voltage from a first voltage; and
    • a second charge pump circuit configured to generate a third voltage from the second voltage;
    • wherein a frequency of a clock signal supplied to the second charge pump circuit is changed in accordance with a control signal, and the frequency is changed to one obtained by dividing an original frequency.

Multi-Patent Capsules

• Patent Identification: U.S. Patent No. 8,519,778, "Semiconductor Integrated Circuit and Booster Circuit Including the Same," issued August 27, 2013 Compl. ¶24

• Technology Synopsis: The patent addresses the problem of high-frequency noise generated during the operation of driver circuits in semiconductor devices Compl. ¶26 The proposed solution is a circuit design, including two inverters and a current source with a current amount independent of the primary voltage, that enables gradual transistor switching to reduce the rate of current change and thereby mitigate high-frequency noise '778 Patent, abstract '778 Patent, col. 2:37-44

• Asserted Claims: At least Claim 1 Compl. ¶85

• Accused Features: The semiconductor integrated circuits within Accused DRAM Modules, such as the Micron DDR5 Y52K DRAM devices, are alleged to infringe Compl. ¶85 Compl. ¶88

• Patent Identification: U.S. Patent No. 8,593,888, "Semiconductor Memory Device," issued November 26, 2013 Compl. ¶28

• Technology Synopsis: The patent seeks to reduce circuit area in semiconductor memory devices by using a single regulator for two different purposes: regulating the drain voltage and regulating the gate voltage of a memory cell '888 Patent, abstract '888 Patent, col. 1:35-44 It achieves this through a switching mechanism that couples the regulator's output to either a voltage applying transistor (for the drain voltage path) or directly to the memory cell gate, depending on the operational mode Compl. ¶29 '888 Patent, col. 2:1-4

• Asserted Claims: At least Claim 1 Compl. ¶102

• Accused Features: The semiconductor memory device structures within Accused DRAM Modules, such as the Micron DDR5 Y52K devices, are alleged to infringe Compl. ¶102 Compl. ¶105

• Patent Identification: U.S. Patent No. 7,777,557, "Booster Circuit," issued August 17, 2010 Compl. ¶32

• Technology Synopsis: This patent, the parent of the '018 Patent, also addresses inefficiency in booster circuits arising from parasitic capacitance '557 Patent, col. 2:12-29 The solution involves an analog comparison circuit that controls the potential of the N-well region based on the output potentials of boosting cells in different rows '557 Patent, abstract '557 Patent, claim 1 This is distinct from the '018 patent's claim to comparing input potentials.

• Asserted Claims: At least Claim 1 Compl. ¶122

• Accused Features: The booster circuits within Accused DRAM Modules, such as the Micron DRAM LPDDR5X Y52P and DDR5 DRAM Y32A die devices, are alleged to infringe Compl. ¶122 Compl. ¶125

III. The Accused Instrumentality

• Product Identification: The complaint identifies two categories of accused products: "Accused DRAM Modules" and "Accused Flash Memory Modules" Compl. ¶¶38-39 Specific examples include Micron LPDDR5X Y52P and DDR5 DRAM Y32A die devices for the '018 and '557 patents; the Micron B47R NAND Flash die together with DRAM devices incorporating the Micron DDR5 Y52K, LPDDR4 Z11M, or LPDDR5 Y42M die for the '231 patent; and Micron DDR5 Y52K DRAM devices for the '778 and '888 patents Compl. ¶41 Compl. ¶63 Compl. ¶85 Compl. ¶102 Compl. ¶122
• Functionality and Market Context: The accused products are fundamental semiconductor memory components, with DRAM serving as volatile memory and NAND as non-volatile memory Compl. ¶36 The complaint alleges that these memory modules are incorporated into a vast array of downstream consumer and enterprise products, while the specific allegations that the accused circuits practice the patented voltage-generation and regulation techniques appear in the patent-specific infringement counts rather than in these general paragraphs Compl. ¶¶36-37 Plaintiff alleges that Defendant is the "only U.S.-based manufacturer of memory chips" and that these products are incorporated into a vast array of consumer and enterprise electronics, including smartphones, servers, and computers Compl. ¶5 Compl. ¶37

No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

7,920,018 Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a first boosting cell row including N stages (N≥1) of the boosting cells; a second boosting cell row including M stages (M≥1) of boosting cells	The accused products' booster circuit is comprised of two rows of boosting cells, with each row containing at least one boosting cell.	¶45	col. 11:58-61
at least one analog comparison circuit for outputting a well bias potential generated by an input potential of the boosting cell on the i-th stage...and an input potential of the boosting cell on the i-th stage...	The accused booster circuit is comprised of at least one analog comparison circuit. The well bias potential is generated by an input potential of a boosting cell in each of the two rows.	¶46	col. 11:62-67
each boosting cell includes a first-conductivity type first well region on a substrate, a second-conductivity type second well region in the first well region, and at least one switching element...	Each boosting cell in the accused product includes a first well region of one conductivity type, a second well region of another conductivity type in the first well region, and one or more switching elements.	¶47	col. 12:1-5
the at least one switching element is configured to transfer charges from a first terminal to a second terminal	The switching elements in the accused product's booster circuit transfer charges from one terminal to another terminal.	¶48	col. 12:6-7
the well bias potential of the at least one analog comparison circuit is applied to the first well region of the switching element included in the at least one boosting cell of the first and second boosting cell rows	The well bias potential of the analog comparison circuit is applied to the first well region of the switching element in the boosting cells of the two rows.	¶49	col. 12:8-11

• Identified Points of Contention:
  • Scope Questions: Claim 1 requires a comparison of the input potential of the boosting cells. Its parent, the '557 Patent, claims comparison of the output potential. The infringement analysis may turn on whether the accused products' analog comparison circuit Compl. ¶46 operates on a signal that can be properly construed as an "input potential" as distinct from an "output potential."
  • Technical Questions: The complaint alleges the presence of an "analog comparison circuit" that generates a "well bias potential" Compl. ¶46 A key evidentiary question will be whether the accused products contain a circuit that structurally and functionally performs this specific comparison and application, or if the underlying mechanism for well biasing operates on a different principle.

7,969,231 Infringement Allegations

Claim Element (from Independent Claim 3)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a first charge pump circuit configured to generate a second voltage from a first voltage;	The accused internal voltage generating circuit contains a charge pump circuit which generates a second voltage from an initial voltage.	¶67	col. 10:19-20
a second charge pump circuit configured to generate a third voltage from the second voltage;	The accused circuit contains a second charge pump circuit which generates a third voltage from the second voltage.	¶67	col. 10:21-22
a frequency dividing circuit configured to divide a first clock signal to generate a second clock signal; and	The accused circuit contains a frequency dividing circuit which divides an initial clock signal to generate a second clock signal.	¶67	col. 10:23-24
a buffer circuit configured to select the first clock signal or the second clock signal and generate a third clock signal,	The accused circuit contains a buffer circuit which generates a third clock signal from the first or the second.	¶67	col. 10:25-26
wherein the third clock signal is supplied to the second charge pump circuit.	Within the accused internal voltage generating circuit, the third clock signal is supplied to the second charge pump circuit.	¶68	col. 10:27-28

• Identified Points of Contention:
  • Technical Questions: The complaint's allegations are conclusory, stating that the accused device "contains four circuits" that map directly to the claim's elements Compl. ¶67 A central dispute will be factual: do the accused products contain physically and functionally distinct "frequency dividing" and "buffer" circuits, or is the clock signal management achieved through an integrated or different architecture that does not meet the claim's structural requirements?
  • Scope Questions: The interpretation of "buffer circuit configured to select" will be critical. The court will need to determine if this requires a specific type of multiplexing circuit, as may be suggested by embodiments in the patent, or if it can be read more broadly to cover any mechanism that effectively switches the clock source for the second charge pump.

V. Key Claim Terms for Construction

For the '018 Patent

• The Term: "input potential of the boosting cell"
• Context and Importance: The distinction between "input potential" and "output potential" is central to the novelty of the '018 Patent relative to its parent, the '557 Patent. Infringement of Claim 1 hinges on whether the potential being compared in the accused circuit is properly characterized as an "input" potential of a boosting cell stage.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The shared specification with the '557 patent describes the invention more generally as fixing the N-well potential to the "input or output potential of the boosting cell stage" '557 Patent, col. 2:38-39 Plaintiff may argue "input potential" should be read in this broader context of a stage-level potential.
  • Evidence for a Narrower Interpretation: The claim language itself is specific. The specification explicitly contemplates different configurations, including one for outputting the higher or lower of an input potential and another for an output potential, suggesting the terms are distinct and not interchangeable '018 Patent, col. 3:7-16

For the '231 Patent

• The Term: "buffer circuit configured to select the first clock signal or the second clock signal"
• Context and Importance: This term recites both a structure ("buffer circuit") and its function ("select"). The infringement analysis will depend on whether the accused products contain a single component that performs both roles. Practitioners may focus on this term because the infringement dispute may turn on whether the accused products contain a "buffer circuit" as claimed or instead use a different mechanism for clock selection.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: Plaintiff may argue that the claim recites the buffer circuit in functional terms-"configured to select the first clock signal or the second clock signal"-without reciting a particular circuit topology, which could support construing the term as a functional block rather than a specific structure '231 Patent, col. 4:25-34
  • Evidence for a Narrower Interpretation: The patent depicts the buffer circuit as a specific arrangement of logic gates designed to perform the selection '231 Patent, FIG. 3 Defendant may argue that this embodiment limits the claim to this structure or its direct equivalents, precluding broader functional interpretations.

VI. Other Allegations

• Indirect Infringement: Plaintiff alleges induced infringement for all asserted patents. The factual basis for inducement includes Defendant allegedly encouraging customers to use the accused products through its sales and technical staff, tailoring products for customer needs, and providing ongoing technical support and firmware updates Compl. ¶¶52-53 Compl. ¶¶75-76 Compl. ¶¶93-94 Compl. ¶¶113-114 Compl. ¶¶132-133 Separately, the complaint pleads contributory infringement under 35 U.S.C. § 271(c) for every asserted patent, alleging that the accused booster and voltage-generation circuits constitute a material part of each claimed invention and are not staple articles or commodities suitable for substantial non-infringing use Compl. ¶57 Compl. ¶81 Compl. ¶98 Compl. ¶118 Compl. ¶137
• Willful Infringement: The complaint alleges willful infringement for all patents. For U.S. Patent Nos. 7,920,018 and 7,777,557, the willfulness claim is based on alleged pre-suit knowledge since at least September 30, 2011, when Defendant was allegedly assigned a patent application that identified the '557 Patent's application as prior art Compl. ¶58 Compl. ¶138 For the remaining patents, the willfulness claim is based on knowledge acquired no later than the filing of the initial complaint on June 30, 2025 Compl. ¶82 Compl. ¶99 Compl. ¶119
• Requested Relief: The complaint's prayer for relief seeks declarations of direct, induced, and contributory infringement; damages, including lost profits and/or a reasonable royalty and treble damages for willful infringement; pre- and post-judgment interest and costs under 35 U.S.C. § 284; a determination that the case is exceptional and an award of attorneys' fees under 35 U.S.C. § 285; supplemental and ongoing royalties; and injunctive relief Compl., Prayer for Relief ¶¶A-H

VII. Analyst's Conclusion: Key Questions for the Case

1. A Question of Definitional Precision: A core issue for the '018 and '557 patents will be whether the accused circuits use a comparison of "input potential" (as claimed in the '018 patent) versus "output potential" (as claimed in the '557 patent). The case may turn on the court's construction of these terms and the technical evidence showing which specific potential is measured in the accused devices.

2. An Evidentiary Question of Structural Equivalence: For patents like '231, '778, and '888, the complaint alleges that the accused products contain structural blocks that map directly to claim elements (e.g., a "frequency dividing circuit," a "current source," a "regulator"). A key dispute will be factual, centering on whether reverse engineering of the accused chips reveals circuits that are structurally and functionally equivalent to those claimed, or if the accused products achieve similar results through fundamentally different technical means.

3. A Question of Pre-Suit Knowledge: The allegation that Defendant knew of the '018 and '557 patents since 2011, based on a patent prosecution event, raises a significant question regarding willful infringement. The court will need to determine if this citation in a related prosecution is sufficient to establish that Defendant possessed the requisite knowledge and intent for a finding of willfulness and potential enhanced damages.