DCT

1:26-cv-01014

Micron Technology Inc v. Netlist Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:26-cv-01014, D. Del., 08/10/2026
  • Venue Allegations: Venue is asserted as proper in the District of Delaware because Defendant Netlist, Inc. is a Delaware corporation and is subject to personal jurisdiction in the district.
  • Core Dispute: Plaintiff seeks a declaratory judgment that its DDR5 memory module products do not infringe three of Defendant's patents related to memory module operation, timing, and testing.
  • Technical Context: The technology concerns high-performance computer memory modules (DIMMs), focusing on methods to manage signal timing integrity and perform testing as operating speeds and densities increase.
  • Key Procedural History: The complaint details a long history of litigation between the parties, alleging that Netlist has pursued a "litigation campaign" against Micron and other suppliers of JEDEC standard-compliant memory modules. Several Netlist patents previously asserted against Micron have reportedly been invalidated in inter partes review and post-grant review proceedings. The complaint notes that Netlist sent letters to Micron in 2021 alleging infringement of the patents-in-suit. It also references other ongoing litigation involving the same patents against Samsung and a separate case against Micron filed in the Central District of California on the same day as the present complaint. Notably, a Markman (claim construction) hearing was held in a related case involving the '523 patent, suggesting that claim construction may be a significant issue in this dispute.

Case Timeline

Date Event
2008-04-14 '523 Patent Earliest Priority Date
2013-07-27 '632 and '407 Patents Earliest Priority Date
2014-03-29 '523 Patent Application Filing Date
2015-04-22 '632 Patent Notice of Allowance Issued
2015-09-08 U.S. Patent 9,128,632 Issues
2018-10-16 '523 Patent Notice of Allowance Issued
2019-02-26 U.S. Patent 10,217,523 Issues
2021-04-28 Netlist sends letter to Micron alleging infringement of '523 and '632 patents
2021-05-19 Netlist sends follow-up letter to Micron
2022-02-07 Netlist asserts '523 patent against Samsung DDR4 LRDIMMs
2023-10-26 Markman hearing held in D. Del. case involving the '523 patent
2024-11-01 '407 Patent Application Filing Date
2026-04-08 '407 Patent Notice of Allowance Issued
2026-07-06 Netlist asserts '407 patent against Samsung DDR5 DIMMs
2026-07-07 U.S. Patent 12,675,407 Issues
2026-08-10 Micron files this Declaratory Judgment Complaint

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,128,632 - "Memory Module With Distributed Data Buffers And Method Of Operation"

Issued September 8, 2015

The Invention Explained

  • Problem Addressed: In high-speed memory modules, control signals sent from a central module controller to distributed buffer circuits can arrive at different times due to varying path lengths, causing timing misalignments (skew) and potential data errors '632 Patent, col. 9:1-14 Conventional methods for managing timing are insufficient for these distributed architectures '632 Patent, col. 2:14-24
  • The Patented Solution: The invention describes a memory module where each distributed buffer circuit locally determines a time interval based on signals received during a memory write operation. This locally derived time interval is then used to time the transmission of read data during a subsequent read operation '632 Patent, abstract '632 Patent, col. 6:4-14 This allows each buffer to self-adjust its read timing to compensate for signal skews, ensuring that data from all buffers arrives at the memory controller in substantial alignment.
  • Technical Importance: This approach provides a decentralized method for timing synchronization on high-speed, high-density memory modules, potentially improving reliability without complex system-level recalibration.

Key Claims at a Glance

  • The complaint asserts non-infringement of claims 1, 6, and 12, with a focus on independent claim 1 Compl. ¶35
  • Independent Claim 1 includes these essential elements:
    • A memory module with a module control device, memory devices in groups, and a plurality of buffer circuits.
    • The buffer circuits are distributed across the module's surface, causing module control signals to arrive at different times.
    • Each buffer circuit is configured to determine a respective time interval based on signals received by that buffer circuit during a memory write operation.
    • Each buffer circuit is further configured to time transmission of a respective set of read data signals in accordance with the determined time interval and a system read latency parameter.
  • The complaint does not explicitly reserve the right to assert non-infringement of dependent claims.

U.S. Patent No. 10,217,523 - "Multi-Mode Memory Module With Data Handlers"

Issued February 26, 2019

The Invention Explained

  • Problem Addressed: The patent's background describes that fully testing memory chips and modules is costly, complex, and time-consuming, and that existing methods using external test hardware or embedded self-test logic have significant limitations and expense '523 Patent, col. 2:3-29
  • The Patented Solution: The patent proposes a memory module that can operate in multiple modes, including a "normal mode" and a "test mode" '523 Patent, abstract In the normal mode, the module functions conventionally, passing data between the on-board memory devices and the system's memory controller. In the test mode, an on-module control module and data module generate test signals and isolate the memory devices from the system controller, allowing the module to perform self-testing without external equipment '523 Patent, col. 2:40-49 Figure 3 illustrates the components involved in the test mode, including a test controller (36) and data handler logic elements (46) '523 Patent, Fig. 3
  • Technical Importance: This design integrates test functionality directly onto the memory module, potentially reducing the reliance on expensive external testers and simplifying system-level validation.

Key Claims at a Glance

  • The complaint asserts non-infringement of claims 1 and 19, with a focus on independent claim 1 Compl. ¶43
  • Independent Claim 1 includes these essential elements:
    • A memory module with memory devices, a data module, and a control module.
    • The module is operable in a first mode and a second mode.
    • In the first mode, the control module passes signals from the system memory controller to the memory devices, and the data module propagates data between them.
    • In the second mode, the control module outputs its own signals, and the data module isolates the memory devices from the system memory controller and transmits data patterns from on-module "data handler logic elements" to the memory devices.
  • The complaint does not explicitly reserve the right to assert non-infringement of dependent claims.

U.S. Patent No. 12,675,407 - "Memory Module With Local Clock Signals"

Issued July 7, 2026

Technology Synopsis

The patent addresses the challenge of distributing a high-speed clock signal across a dense memory module with consistent timing '407 Patent, col. 2:6-18 It proposes circuitry on the module that generates a plurality of local clocks, one for each group of memory devices, where the phase of each local clock is independently programmable relative to the main system clock '407 Patent, abstract

Asserted Claims

The complaint asserts non-infringement of independent claims 1 and 6 Compl. ¶51

Accused Features

Micron alleges its DDR5 products do not infringe because they do not "generate a plurality of local clocks having respective phase relationships with the system clock, the respective phase relationships being programmable independently of each other" and do not output a respective local clock to a corresponding group of memory devices and "not to any other group" as claimed Compl. ¶53

III. The Accused Instrumentality

Product Identification

Micron's DDR5 products, including but not to limited to DIMM, RDIMM, LRDIMM, NVDIMM, and MRDIMM products Compl. ¶4 Compl. ¶6 Compl. ¶9 Compl. ¶36

Functionality and Market Context

  • The complaint describes the accused products as JEDEC standard-compliant memory modules used in computer systems Compl. ¶4 Compl. ¶19 These products serve as high-speed, high-density system memory.
  • The complaint does not provide detailed technical specifications of the accused products' internal operations. Instead, it makes conclusory statements that the products do not incorporate the technologies claimed in the patents-in-suit Compl. ¶37 Compl. ¶45 Compl. ¶53
  • Micron positions itself as "the only United States founded memory semiconductor designer and manufacturer" and a "world leader in innovative computer-memory and data-storage solutions" Compl. ¶2

IV. Analysis of Infringement Allegations

No probative visual evidence provided in complaint.

'9,128,632 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Non-Infringing Functionality Complaint Citation Patent Citation
...wherein the each respective buffer circuit is configured to determine a respective time interval based on signals received by the each respective buffer circuit during a memory write operation... Micron's DDR5 products do not satisfy this claim element Compl. ¶37 The complaint does not specify how the products' functionality differs from this limitation. ¶37 col. 18:50-55
...and is further configured to time transmission of a respective set of read data signals received from the respective group of memory devices in accordance with the time interval and a read latency parameter of the memory system during a memory read operation. Micron's DDR5 products do not satisfy this claim element Compl. ¶37 The complaint does not specify how the products' functionality differs from this limitation. ¶37 col. 18:55-65
  • Identified Points of Contention ('632 Patent):
    • Technical Question: The central dispute appears to be a factual and technical one: do Micron's DDR5 products employ a mechanism that "determine[s] a respective time interval" during a write operation to then "time transmission" of read data? The complaint provides no technical evidence, so a key question for the court will be what timing mechanisms are actually used in the accused products and whether they function as required by the claim.

'10,217,523 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Non-Infringing Functionality Complaint Citation Patent Citation
...wherein the memory module is operable in any of a plurality of modes including a first mode and a second mode; Micron's DDR5 products do not satisfy this and the following claim elements Compl. ¶45 The complaint does not provide technical details on the products' operational modes. ¶45 col. 17:1-3
wherein the control module in the first mode is configured to receive system address and control signals from the system memory controller and to output first memory address and control signals to the memory devices... and the data module in the first mode is configured to propagate one or more first data signals between the memory devices and the system memory controller... Micron's DDR5 products do not satisfy this claim element Compl. ¶45 ¶45 col. 17:4-16
wherein the control module in the second mode is configured to output second memory address and control signals... and the data module in the second mode is configured to isolate the memory devices from being accessed by the system memory controller and to transmit one or more second data signals including data patterns provided by the data handler logic elements... Micron's DDR5 products do not satisfy this claim element Compl. ¶45 ¶45 col. 17:17-31
  • Identified Points of Contention ('523 Patent):
    • Scope Question: A primary issue will be whether any diagnostic or test functions present in Micron's standard-compliant DDR5 products fall within the scope of the claimed "second mode." This raises the question of whether standard JEDEC-defined features can be construed as meeting the claim's specific requirements.
    • Technical Question: Does any function in the accused products perform the claimed actions of the "second mode," specifically to "isolate the memory devices from being accessed by the system memory controller" while simultaneously using on-module "data handler logic elements" to transmit test patterns? The analysis will likely focus on the degree of isolation and the origin of any test patterns used.

V. Key Claim Terms for Construction

  • '632 Patent

    • The Term: "determine a respective time interval"
    • Context and Importance: This term is the core of the asserted independent claim's point of novelty and the basis for Micron's non-infringement argument Compl. ¶37 The interpretation of "determine" will be critical. Practitioners may focus on whether this term requires an active calculation or measurement process within the buffer circuit, or if it could be construed more broadly to cover a passive or inherent delay.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification describes using the time interval to "adjust the timing of the transmission of read data" '632 Patent, col. 10:29-34 This could suggest any mechanism that results in a timed adjustment, even a fixed one, might be considered.
      • Evidence for a Narrower Interpretation: The claim requires the determination to be "based on signals received by the each respective buffer circuit during a memory write operation" ('632 Patent, col. 18:52-55). This language, along with flowcharts showing a process of receiving signals and generating a delay signal '632 Patent, Fig. 18, may support an interpretation requiring an active, dynamic process where the interval is ascertained during each relevant operation.

  • '523 Patent

    • The Term: "isolate the memory devices from being accessed by the system memory controller"
    • Context and Importance: This term defines a key function of the "second mode" and is central to distinguishing it from normal operation. The complaint mentions a Markman hearing in a related case, suggesting claim construction is a known point of dispute Compl. ¶7 The meaning of "isolate" will determine whether standard diagnostic features can be considered infringing.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The patent states the data module "enables data paths between the memory devices and the system memory controller" in the normal mode '523 Patent, abstract This could imply that "isolate" simply means to disable those paths, a function that might occur in various standard operating states.
      • Evidence for a Narrower Interpretation: The abstract contrasts the "test mode," where the data module "isolates the memory devices," with the "normal mode." The detailed description explains that in the test mode, the data module "isolates the data path from the system board" '523 Patent, col. 5:35-40 This suggests a specific action tied to the test mode, potentially requiring a more complete logical or physical separation than what might be found in standard power-saving or idle modes.

VI. Other Allegations

  • Indirect Infringement: The complaint seeks a declaration that Micron is not liable for indirect infringement under 35 U.S.C. § 271(b)-(c) Compl. ¶40 Compl. ¶48 Compl. ¶56 The basis for this request is the assertion that because Micron's products do not directly infringe, there can be no secondary liability.
  • Willful Infringement: The complaint does not allege willfulness but seeks a declaration of non-liability for all damages Compl., Prayer for Relief ¶(a) The facts alleged in the complaint, specifically the receipt of letters from Netlist in 2021 alleging infringement of the '632 and '523 patents, establish pre-suit knowledge Compl. ¶5 This documented knowledge could form the basis of a willfulness counterclaim by Netlist should it assert infringement.

VII. Analyst's Conclusion: Key Questions for the Case

This declaratory judgment action presents several key questions for the court that center on the intersection of claim scope and the functionality of industry-standard products.

  • A central technical question will be one of functional operation: Do Micron's DDR5 products, in their normal operation, perform the specific two-step process required by the '632 patent-first "determin[ing] a... time interval" from a write operation and then using that same interval to "time transmission" of a read operation? The case may turn on evidence demonstrating whether or not this specific cause-and-effect timing mechanism exists in the accused devices.
  • A core issue of definitional scope will drive the analysis of the '523 patent: Can the claimed "second mode," which requires "isolat[ing] the memory devices" and using on-module logic to generate test patterns, be interpreted to read on standard diagnostic or self-refresh states found in JEDEC-compliant memory modules? The outcome will likely depend on the construction of "isolate" and whether the accused products' functions match the specific architecture claimed.
  • A significant overarching question relates to patent validity in context: Given the complaint's emphasis on Netlist's history of litigation and the subsequent invalidation of other asserted patents by the USPTO Compl. ¶4, a critical issue will be whether the '632, '523, and '407 patents can withstand the validity challenges (e.g., for obviousness or lack of enablement) that Micron is likely to bring in a counterclaim.
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