DCT

1:26-cv-00650

Samsung Electronics Co Ltd v. Netlist Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: Samsung Electronics Co., Ltd. v. Netlist, Inc., 1:26-cv-00650, D. Del., 07/14/2026
  • Venue Allegations: Venue is alleged to be proper in the District of Delaware because Defendant Netlist, Inc. is a Delaware corporation and is subject to personal jurisdiction in the district.
  • Core Dispute: Plaintiffs seek a declaratory judgment that their memory products do not infringe two Netlist patents, that one patent is unenforceable due to inequitable conduct, and, alternatively, that Netlist has breached its contractual obligations to license the patents on reasonable and non-discriminatory (RAND) terms.
  • Technical Context: The technology concerns high-performance computer memory modules, such as High Bandwidth Memory (HBM) and Dual In-line Memory Modules (DIMMs), focusing on methods for managing electrical load in stacked-chip packages and for signaling between a memory module and a system controller.
  • Key Procedural History: The complaint details extensive prior litigation between the parties in U.S. District Courts and the International Trade Commission (ITC) involving related patents. It also cites numerous inter partes review (IPR) and post-grant review (PGR) proceedings before the U.S. Patent and Trademark Office, some of which resulted in the invalidation or disclaimer of claims in patents from the same families as the patents-in-suit. A central element of the dispute is an ongoing disagreement over the status of a 2015 Joint Development and License Agreement (JDLA) and Netlist's alleged RAND licensing obligations as a member of the JEDEC standards-setting organization.

Case Timeline

Date Event
2009-06-12 '937 Patent Priority Date
2010-11-03 '537 Patent Priority Date
2015-11-12 Samsung and Netlist enter into Joint Development and License Agreement (JDLA)
2020-07-15 Netlist writes to Samsung to terminate the JDLA
2020-10-15 Netlist issues a "Notice of Infringement" to Samsung
2021-10-15 Samsung files IPR petitions for patents related to the '937 patent
2021-12-20 Netlist begins patent litigation campaign against Samsung in E.D. Tex.
2022-08-26 Samsung files IPR petitions for patents related to the '537 patent
2024-04-01 PTAB invalidates all claims of two patents related to the '537 patent family
2025-08-25 Samsung files PGR petition for the parent of the '537 patent
2025-09-30 Netlist files ITC complaint against Samsung alleging infringement by HBM and DIMM products
2026-02-18 PTAB institutes PGR on the parent of the '537 patent
2026-06-02 U.S. Patent No. 12,646,537 ('537 Patent) issues
2026-06-02 Netlist sues Samsung in E.D. Tex. for infringement of the '537 Patent
2026-06-09 U.S. Patent No. 12,650,937 ('937 Patent) issues
2026-06-09 Netlist sues Samsung and Avnet in E.D. Tex. for infringement of the '937 Patent
2026-07-14 Complaint for Declaratory Judgment filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 12,646,537 - "Memory Package Having Stacked Array Dies and Reduced Driver Load"

  • Patent Identification: U.S. Patent No. 12,646,537, "Memory Package Having Stacked Array Dies and Reduced Driver Load," issued June 2, 2026.

The Invention Explained

  • Problem Addressed: In memory packages with vertically stacked semiconductor dies, a single driver sending signals to all dies faces a significant electrical load. Overcoming this load requires a larger driver, which consumes more space and power on the control die. Compl. ¶84 '537 Patent, col. 2:27-34
  • The Patented Solution: The invention divides the stack of memory dies into at least a "first plurality" and a "second plurality." It uses separate, dedicated interconnects (e.g., through-silicon vias) and associated drivers for each plurality. For instance, a first driver and interconnect serve only the first group of dies, while a second driver and interconnect serve only the second group. This partitioning of the signal paths reduces the load on any individual driver, allowing for smaller, more power-efficient drivers. Compl. ¶85 '537 Patent, abstract '537 Patent, col. 5:60-65 The complaint includes Figure 2 from the patent, which depicts a stack of four array dies (210a-210d) divided into two pairs, each served by separate interconnects (220a, 220b). Compl. p. 25, FIG. 2
  • Technical Importance: This load-reduction technique is designed to improve the power efficiency and density of high-capacity, 3D-stacked memory architectures like High Bandwidth Memory (HBM). Compl. ¶34 Compl. ¶84

Key Claims at a Glance

  • The complaint asserts non-infringement of independent claims 1, 8, and 14. Compl. ¶129
  • The essential elements of independent claim 1 include:
    • A DRAM package with an interface, stacked DRAM dies, a control die, and die interconnects.
    • The stacked DRAM dies include a "first plurality" and a "second plurality" of DRAM dies.
    • The die interconnects include "first die interconnects" for the first plurality and "second die interconnects" for the second plurality.
    • The "first plurality of DRAM dies are configured to not receive or output any signals via any of the second die interconnects."
    • The "second plurality of DRAM dies are configured to not receive or output any signals via any of the first die interconnects."
    • The control die includes signal conduits (e.g., drivers) that "concurrently drive" data signals to the respective first and second data interconnects.
  • The complaint states that Plaintiffs' non-infringement position applies to all dependent claims as well. Compl. ¶134

U.S. Patent No. 12,650,937 - "Memory Module Operable to Provide Distinct Signaling Interfaces Via an Open-Drain Output for Distinct Operations"

  • Patent Identification: U.S. Patent No. 12,650,937, "Memory Module Operable to Provide Distinct Signaling Interfaces Via an Open-Drain Output for Distinct Operations," issued June 9, 2026.

The Invention Explained

  • Problem Addressed: The patent describes that conventional computer systems lacked an efficient "handshaking" mechanism between the system memory controller (MCH) and a memory module during initialization. The MCH would have to blindly wait for a predetermined period for the module to complete its tasks, an inefficient process. Compl. ¶89 '937 Patent, col. 1:55-67
  • The Patented Solution: The invention uses an open-drain output on the memory module to create two distinct signaling interfaces. One is a "feedback path" used during initialization to send signals related to initialization sequences, notifying the MCH when tasks are complete. The other is a "signaling interface" used during normal operation to report events like parity errors. This allows the MCH to receive positive confirmation of initialization progress rather than blindly waiting. (Compl. ¶88; Compl. ¶89; Compl. ¶90; Compl. ¶91; Compl. ¶92, Compl. ¶abstract; '937 Patent, Compl. ¶¶col. 2:1-12). The complaint includes Figure 1 from the patent, which illustrates a system memory controller (14) connected to a memory module (10) that has a notification circuit (20) driving an output (12). Compl. p. 26, FIG. 1
  • Technical Importance: This handshaking method enables more efficient system startup procedures, particularly in complex server systems with multiple memory modules that may have different initialization timings. Compl. ¶89 '937 Patent, col. 1:62-67

Key Claims at a Glance

  • The complaint asserts non-infringement of independent claims 1, 11, and 17. Compl. ¶140
  • The essential elements of independent claim 1 include:
    • A memory subsystem with a printed circuit board, DRAM elements, and a memory subsystem controller.
    • The controller has an open-drain output providing a "signaling interface" for normal operations and a "feedback path" for initialization.
    • The controller is operable to output, via the feedback path, a "first signal related to a first part of the initialization operation sequences" and "subsequently a second signal related to a second part."
    • The "second part of the initialization operation sequences being distinct from the first part."
    • During initialization, the memory subsystem is not operable to respond to C/A signals by outputting or receiving data.
  • The complaint states that Plaintiffs' non-infringement position applies to all dependent claims as well. Compl. ¶144

III. The Accused Instrumentality

Product Identification

  • The complaint names two categories of accused products:
    • For the '537 Patent: Samsung High Bandwidth Memory (HBM) products, including HBM2, HBM2E, HBM3, HBM3E, HBM4, and newer versions. Compl. ¶25 Compl. ¶86
    • For the '937 Patent: Samsung DDR5 DIMM Products, specifically DDR5 Registered Dual In-line Memory Modules (RDIMMs). Compl. ¶26 Compl. ¶94

Functionality and Market Context

  • The complaint describes the accused HBM products as featuring a "wide-interface architecture" where different channels can be accessed in parallel. Compl. ¶132 HBM is a key technology for high-performance computing and artificial intelligence applications. Compl. ¶34
  • The complaint describes the accused Samsung DIMM Products as using a process called "Clock-to-CA training" during initialization, which involves the use of an "Alert_n" pin. Compl. ¶143 DDR5 is the latest generation of mainstream memory for servers and PCs, and compliance with industry standards like those from JEDEC is alleged to be critical for commercial viability. Compl. ¶¶96-97

IV. Analysis of Infringement Allegations

'537 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Non-Infringing Functionality Complaint Citation Patent Citation
the first plurality of DRAM dies are configured to not receive or output any signals via any of the second die interconnects; In the Samsung HBM Products, the group of dies corresponding to the claimed "first plurality of DRAM dies" allegedly receives signals via the interconnects corresponding to the claimed "second die interconnects." ¶131 col. 25:59-62
the second plurality of DRAM dies are configured to not receive or output any signals via any of the first die interconnects. In the Samsung HBM Products, the group of dies corresponding to the claimed "second plurality of DRAM dies" allegedly receives signals via the interconnects corresponding to the claimed "first die interconnects." ¶131 col. 26:1-4
the first C/A conduits and the second C/A conduits are configurable to concurrently drive respective C/A signals to respective die interconnects... The complaint alleges that Netlist's infringement theory relies on the parallel access architecture of the HBM products, but Plaintiffs' position is that this architecture does not meet the specific "concurrently drive" limitation. ¶132 col. 27:20-27
a first die interconnect ... is configurable to be coupled to a first terminal ... via a first conduit, and a second die interconnect ... is configurable to be coupled to the first terminal via a second conduit ... (from dependent claim 14) The Samsung HBM Products allegedly do not have data interconnects that share a single data terminal as required by the claim. ¶133 col. 29:4-10
  • Identified Points of Contention:
    • Technical Question: A central factual dispute will be whether Samsung's HBM architecture implements the strict signal isolation required by the claims. The complaint alleges that, contrary to the claim language, the "first plurality" of dies does receive signals via the "second interconnects," and vice-versa. Compl. ¶131
    • Scope Question: The analysis will likely focus on how the claim terms "first plurality of DRAM dies" and "second plurality of DRAM dies" map onto the physical and logical structure of Samsung's HBM products. The question for the court will be whether the parallel channel architecture of HBM products falls within the scope of the patent's claimed divided-interconnect structure. Compl. ¶132

'937 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Non-Infringing Functionality Complaint Citation Patent Citation
a first signal related to a first part of the initialization operation sequences and subsequently a second signal related to a second part... the second part ... being distinct from the first part... The complaint alleges that in the Samsung DIMM Products, the part of the initialization sequence corresponding to the "second part" is not distinct from the "first part," as required by the claim. ¶142 col. 15:4-16
output[ting] via the feedback path a first signal... and subsequently a second signal... The complaint alleges the accused products' "Alert_n" pin is not used to output a signal related to initialization sequences. Instead, it "loops back" the result of an OR logic function, which is described as implementing a disclaimed "polling method" of handshaking rather than the claimed "notifying method." ¶143 col. 15:3-10
during the initialization operation, the memory subsystem is not operable to respond to any C/A signals from the system memory controller by outputting to, or receiving from, the data signal lines any data signals. The complaint does not provide sufficient detail for analysis of this specific element. ¶141 col. 15:25-30
  • Identified Points of Contention:
    • Technical Question: A key factual question is whether the "Clock-to-CA training" protocol used in Samsung's DIMMs involves sequences that are "distinct" in the manner required by the claim. The complaint argues they are not. Compl. ¶142
    • Scope Question: The infringement analysis will likely turn on the distinction between a "notifying method" and a "polling method." The complaint alleges that the accused "Alert_n" pin implements a "polling method" that was disclaimed during prosecution, which, if true, could preclude infringement under the doctrine of prosecution history estoppel. Compl. ¶143

V. Key Claim Terms for Construction

  • '537 Patent: "configured to not receive or output any signals"

    • Context and Importance: This term is at the core of the non-infringement argument. The patent's architecture relies on strict electrical isolation between the "first plurality" and "second plurality" of dies to achieve load reduction. Whether Samsung's HBM products, which use a parallel channel architecture, meet this negative limitation will be a determinative issue. Compl. ¶131
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation (favoring non-infringement): The plain language of the claim is an absolute negative ("not... any signals"). Plaintiffs may argue this requires complete electrical isolation, which they contend their products lack. Compl. ¶131
      • Evidence for a Narrower Interpretation (favoring infringement): Netlist may argue the term should be interpreted in the context of a specific operational mode, and that "any signals" refers only to the specific data or C/A signals intended for the other plurality, not incidental crosstalk or signals on shared power/ground lines. The specification describes the interconnects as conducting signals to or between specific pluralities, which might support a more functional, rather than absolute, interpretation. '537 Patent, col. 25:46-58

  • '937 Patent: "distinct from the first part of the initialization operation sequence"

    • Context and Importance: This term is critical for determining if the accused DDR5 DIMMs' "Clock-to-CA training" infringes. The patent requires the controller to output signals for at least two "distinct" parts of the initialization. The complaint alleges the accused products' operations are not "distinct," raising the question of what degree of difference is required. Compl. ¶142
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation (favoring non-infringement): The claim language also requires the "second time period being distinct from the first time period and having a different duration." '937 Patent, col. 15:13-16 Plaintiffs may argue that "distinct part" must mean a wholly separate and non-overlapping type of operation, which they allege is not the case in their products. Compl. ¶142
      • Evidence for a Narrower Interpretation (favoring infringement): The specification provides examples of different training sequences that could occur during initialization. Netlist may argue that any two sequential, functionally different steps in an initialization protocol constitute "distinct parts," even if they are part of a larger, single-named process like "Clock-to-CA training." '937 Patent, col. 3:9-14

VI. Other Allegations

  • Inequitable Conduct and Unclean Hands ('537 Patent): The complaint alleges that the '537 patent is unenforceable due to inequitable conduct. Compl. ¶¶148-169 The basis is an allegedly false "Request Not to Publish" certification filed with the USPTO during the patent's prosecution. Compl. ¶154 The certification stated the application's invention had not been part of a prior international application requiring publication. Compl. ¶154 The complaint alleges this was false, as the invention was disclosed in a published PCT application (WO 2012/061633 A2). Compl. ¶157 It is alleged this was done willfully and with intent to deceive the USPTO to gain a strategic litigation advantage by preventing the public and litigation targets from viewing the claims before the patent issued. (Compl. ¶¶162; Compl. ¶164).
  • Breach of Contract (RAND Obligations): As an alternative to non-infringement, the complaint alleges that if the patents are found to be essential to JEDEC standards for HBM or DIMM products, Netlist has breached its contractual commitment to license them on RAND terms. (Compl. ¶¶171; Compl. ¶182). The complaint alleges Netlist is a member of JEDEC and is bound by its patent policy. (Compl. ¶¶102; Compl. ¶115). The alleged breach consists of making non-RAND licensing demands to Samsung, including demands for a "new license" after asserting the prior JDLA was terminated. Compl. ¶121 Compl. ¶179

VII. Analyst's Conclusion: Key Questions for the Case

  • A primary issue will be one of enforceability and contract: Will the '537 patent be rendered unenforceable for inequitable conduct based on the allegedly false "Request Not to Publish" certification filed during prosecution? Separately, if either patent is found to be infringed and essential to JEDEC standards, has Netlist breached its RAND licensing obligations, and would such a breach limit its remedies to a RAND royalty rather than an injunction or damages based on a hypothetical negotiation?
  • A key infringement question will be one of technical and definitional scope: For the '537 patent, can the claim language requiring strict signal isolation between two "pluralities" of dies be read onto the parallel, multi-channel architecture of Samsung's HBM products? For the '937 patent, does the "Alert_n" signal in the accused DIMMs function as the claimed "feedback path" for "distinct" initialization sequences, or does it operate as a "polling" method allegedly disclaimed during prosecution?
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