DCT

1:26-cv-00641

Micron Technology Inc v. Netlist Inc

Log In
Key Events
Amended Complaint
complaint Intelligence

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:26-cv-00641, D. Del., 06/30/2026
  • Venue Allegations: Venue is alleged to be proper as Defendant Netlist, Inc. is a Delaware corporation and subject to personal jurisdiction in the district.
  • Core Dispute: Plaintiffs seek a declaratory judgment that their High Bandwidth Memory (HBM) products do not infringe Defendant's patent related to stacked DRAM memory packages, and further ask the court to declare the patent unenforceable due to alleged inequitable conduct during prosecution.
  • Technical Context: The technology concerns high-density memory packages, such as HBM, which stack multiple semiconductor (DRAM) dies vertically to increase memory bandwidth and density, a critical technology for high-performance computing, AI, and graphics processing.
  • Key Procedural History: This declaratory judgment action arises from a history of litigation between the parties. The complaint states that Defendant Netlist previously sued Plaintiff Micron on related patents ('060, '160, '087). It notes that all claims of the '060 and '160 patents were found unpatentable in inter partes reviews (IPRs) and that a post-grant review (PGR) was instituted against the '087 patent. The patent-in-suit ('537 patent) is a recently issued continuation from the same family. The complaint also alleges that Netlist improperly filed a "Request Not to Publish" for the '537 patent application, forming the basis for an inequitable conduct claim.

Case Timeline

Date Event
2010-11-03 '537 Patent Priority Date (Provisional App. 61/409,893)
2011-11-03 International Application PCT/US2011/059209 Filing Date
2012-05-10 International Application WO 2012/061633 Publication Date
2022-06-10 Netlist files suit against Micron on '060 and '160 patents (EDTX-203)
2023-04-12 IPRs filed against '060 and '160 patents
2024-02-10 EDTX-203 case stayed pending IPR resolution
2024-04-01 USPTO finds all challenged claims of '060 and '160 patents unpatentable
2025-05-19 '638 Application (leading to '537 patent) filed
2025-05-19 Netlist files suit against Micron on '087 patent (EDTX-558)
2025-08-25 PGR filed against '087 patent
2026-02-18 USPTO institutes PGR of '087 patent
2026-03-06 EDTX-558 case transferred to District of Delaware
2026-06-02 U.S. Patent No. 12,646,537 issues
2026-06-30 Micron files First Amended Complaint for Declaratory Judgment

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 12,646,537 - "MEMORY PACKAGE HAVING STACKED ARRAY DIES AND REDUCED DRIVER LOAD"

  • Patent Identification: U.S. Patent No. 12,646,537, issued June 2, 2026.

The Invention Explained

  • Problem Addressed: The patent's background section describes a problem in stacked memory packages where increasing the number of vertically stacked memory dies (array dies) increases the electrical load on the driver circuits located on a separate control die. This increased load requires larger, more power-hungry drivers, which consume valuable space and power '537 Patent, col. 1:30-34
  • The Patented Solution: The invention proposes to solve this problem by partitioning the stack of DRAM dies into at least two distinct groups ("a first plurality" and "a second plurality") '537 Patent, abstract Each group is serviced by its own dedicated set of electrical "die interconnects" (e.g., through-silicon vias or TSVs) that are electrically isolated from the interconnects serving the other group '537 Patent, col. 6:15-37 By dividing the communication paths this way, the electrical load on any single driver on the control die is reduced, as each driver only needs to service a subset of the total dies in the stack '537 Patent, FIG. 2
  • Technical Importance: This load-partitioning architecture enables the design of higher-density, more power-efficient stacked memory modules, which is a key objective in the development of technologies like High Bandwidth Memory (HBM).

Key Claims at a Glance

  • The complaint focuses on independent claim 1 in its request for a declaration of non-infringement Compl. ¶28
  • The essential elements of independent claim 1 include:
    • A dynamic random access memory (DRAM) package comprising an interface, stacked DRAM dies, a control die, and die interconnects (including TSVs).
    • The stacked DRAM dies include a "first plurality of DRAM dies" and a "second plurality of DRAM dies."
    • The die interconnects are divided into "first die interconnects" and "second die interconnects."
    • The first die interconnects are configured to conduct command/address (C/A) and data signals to/from the first plurality of DRAM dies.
    • The second die interconnects are configured to conduct C/A and data signals to/from the second plurality of DRAM dies.
    • A negative limitation requiring that the first plurality of DRAM dies are configured "to not receive or output any signals via any of the second die interconnects."
    • A corresponding negative limitation requiring that the second plurality of DRAM dies are configured "to not receive or output any signals via any of the first die interconnects."
    • The control die includes signal conduits that concurrently drive signals to the first and second C/A and data interconnects.

III. The Accused Instrumentality

Product Identification

  • Plaintiffs' High Bandwidth Memory ("HBM") products Compl. ¶14

Functionality and Market Context

  • The complaint alleges that these are JEDEC standard-compliant memory modules Compl. ¶16 It states that Netlist has previously accused these products of infringing related patents in prior lawsuits Compl. ¶14 The complaint does not provide specific technical details on the internal architecture or operation of the accused HBM products, focusing instead on a conclusory assertion that they do not meet certain limitations of the asserted claim Compl. ¶30

IV. Analysis of Infringement Allegations

This action is for a declaratory judgment of non-infringement. The table below summarizes the Plaintiff's (Micron's) non-infringement position as articulated in the complaint.

'537 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Plaintiff's Non-Infringement Position Complaint Citation Patent Citation
"die interconnects [that] include first die interconnects...configured to conduct C/A signals from the control die to [a] first plurality of DRAM dies and the first data interconnects are configured to conduct data signals between the control die and the first plurality of DRAM dies; the die interconnects further include second die interconnects...configured to conduct C/A signals from the control die to [a] second plurality of DRAM dies, and the second data interconnects are configured to conduct data signals between the control die and the second plurality of DRAM dies; the first plurality of DRAM dies are configured to not receive or output any signals via any of the second die interconnects; the second plurality of DRAM dies are configured to not receive or output any signals via any of the first die interconnects." (Elements 1.g-1.j) The complaint alleges that "Micron's HBM products do not satisfy these claim elements." ¶30 col. 6:15-37

Identified Points of Contention

  • Technical Question: The primary dispute appears to be factual and technical: Do Micron's HBM products actually implement the partitioned architecture required by claim 1? The complaint provides no specific evidence to support its assertion of non-infringement. The resolution of this question will likely depend on expert analysis of the physical layout and electrical pathways within Micron's HBM devices to determine if they contain the distinct and isolated "first die interconnects" and "second die interconnects" for separate "pluralities" of DRAM dies as claimed.
  • Scope Questions: The case raises the question of what degree of electrical isolation is required by the negative limitations "configured to not receive or output any signals." A court may need to construe whether this requires absolute electrical isolation or merely the absence of an intended signaling path, potentially allowing for incidental crosstalk or coupling.

V. Key Claim Terms for Construction

  • The Term: "first plurality of DRAM dies" and "second plurality of DRAM dies"

    • Context and Importance: The claim's central inventive concept is the partitioning of the DRAM stack into these distinct "pluralities," each serviced by isolated interconnects. The definition of what constitutes a "plurality" in this context is therefore critical. Practitioners may focus on this term because the entire non-infringement argument rests on whether the accused products are architected with such a partitioned structure.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification describes the "plurality of array dies 210 (e.g., array dies 210a-210d)" without imposing strict rules on how they are grouped, which may support an interpretation that any grouping of two or more dies can constitute a "plurality" '537 Patent, col. 5:40-43
      • Evidence for a Narrower Interpretation: The patent's figures, such as FIG. 2, depict the pluralities as distinct, physically adjacent sub-stacks (e.g., dies 210a and 210b form one group, while 210c and 210d form another) '537 Patent, FIG. 2 A party could argue this embodiment limits the term to such physically organized groupings.

  • The Term: "configured to not receive or output any signals"

    • Context and Importance: This negative limitation, appearing in elements 1.i and 1.j, defines the required isolation between the die interconnects for the different pluralities. Its interpretation will be pivotal in determining infringement. If Micron's products have any level of electrical coupling between signal paths for different die groups, the meaning of "not receive...any signals" will be dispositive.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation (favors patentee): A party may argue "signals" refers to intentionally transmitted data or command/address signals, and that the limitation does not preclude incidental electrical phenomena like noise or crosstalk.
      • Evidence for a Narrower Interpretation (favors accused infringer): The specification uses the phrase "electrically isolated" when describing the separation between interconnects for different die groups '537 Patent, col. 6:35-37 This may support an argument that the claim requires a high degree of electrical isolation, and the presence of any detectable signal, even unintentional, would mean the limitation is not met.

VI. Unenforceability and Unclean Hands Allegations

The complaint alleges that the '537 patent is unenforceable due to inequitable conduct and unclean hands committed by Netlist during patent prosecution Compl. ¶¶34-53

Inequitable Conduct

Micron alleges that Netlist and its patent counsel, with intent to deceive the U.S. Patent and Trademark Office (USPTO), filed a false certification in a "Request Not to Publish" under 35 U.S.C. § 122(b) Compl. ¶¶39-41 The complaint alleges this was done to conceal the pending application and its claims from litigation targets, thereby gaining a strategic advantage Compl. ¶46

  • The complaint includes a screenshot of the allegedly false certification, in which Netlist certified that the invention "has not and will not be the subject of an application filed in another country...that requires publication" Compl. p. 10
  • This certification was allegedly false because the application claimed priority to, and disclosed the same invention as, an international PCT application that had already been published Compl. ¶41
  • To support the allegation of intent, the complaint provides evidence that the same patent counsel prosecuting the '537 patent application had previously submitted an Information Disclosure Statement (IDS) in a related case that specifically cited the search report for the published international application, suggesting awareness of its existence Compl. ¶44 Compl. p. 12
  • The complaint further includes a side-by-side comparison of figures from the '537 patent's application and the international publication to demonstrate that they disclose the same invention Compl. ¶42 Compl. p. 11

Unclean Hands

Micron alleges that Netlist's conduct, including the allegedly fraudulent non-publication request, constitutes unclean hands that should render the '537 patent unenforceable Compl. ¶53

VII. Analyst's Conclusion: Key Questions for the Case

  1. A core issue will be one of architectural correspondence: does the physical and electrical architecture of Micron's HBM products align with the partitioned structure mandated by Claim 1, where distinct pluralities of DRAM dies are serviced by electrically isolated interconnects, or is there a fundamental operational mismatch as Micron alleges?
  2. A second central issue will be one of prosecution conduct and intent: did Netlist, through its counsel, knowingly submit a false non-publication request to the USPTO with the specific intent to deceive the office and gain a strategic litigation advantage, and if proven, does this conduct rise to the level of inequitable conduct sufficient to render the entire '537 patent unenforceable?
Loading Amended Complaint