DCT

1:26-cv-00592

Edgecomm LLC v. Super Micro Computer Inc

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Key Events
Amended Complaint
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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:26-cv-00592, D. Del., 09/24/2026
  • Venue Allegations: Venue is alleged in the District of Delaware because the defendant, a Delaware corporation, has an established place of business in the district and has allegedly committed acts of infringement there.
  • Core Dispute: Plaintiff alleges that Defendant’s computer products infringe a patent related to using a packet-based serial interface, such as Ethernet, for processor-to-memory communication.
  • Technical Context: The technology addresses the "memory wall" problem in computer architecture, where the speed of communication between a processor and memory lags behind the processing speed of the components themselves, creating a performance bottleneck.
  • Key Procedural History: This is a First Amended Complaint. The complaint alleges that the service of an original complaint put the defendant on actual notice of its alleged infringement.

Case Timeline

Date Event
2008-02-04 '483 Patent Priority Date
2010-10-25 '483 Patent Application Date
2012-07-31 '483 Patent Issue Date
2026-09-24 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,234,483 - "Memory units with packet processor for decapsulating read write access from and encapsulating response to external devices via serial packet switched protocol interface"

  • Patent Identification: U.S. Patent No. 8,234,483, "Memory units with packet processor for decapsulating read write access from and encapsulating response to external devices via serial packet switched protocol interface," issued July 31, 2012.

The Invention Explained

  • Problem Addressed: The patent’s background section describes the performance limitations of traditional computer architectures, where parallel buses (like the Front-Side Bus) that connect processors to memory are slower than the components they serve US 8,234,483 B2, col. 2:30-40 This "memory wall" or "Von Neuman Bottleneck" is exacerbated by issues like clock skew and the large physical space required by parallel buses, which makes it difficult to increase their speed US 8,234,483 B2, col. 2:10-20 US 8,234,483 B2, col. 2:58-68
  • The Patented Solution: The invention proposes replacing the traditional parallel bus with a high-speed, packet-switched serial interface, similar to those used for network I/O like Gigabit Ethernet US 8,234,483 B2, abstract The patent describes a "packet processor" integrated onto the same semiconductor package as a memory device US 8,234,483 B2, col. 11:26-53, claim 1 This processor receives memory access commands (e.g., read, write) from an external device, "decapsulates" them from a serial packet format, and then "encapsulates" the resulting data into a new packet for transmission back to the external device US 8,234,483 B2, col. 11:37-53, claim 1 Figure 2C, for instance, depicts a processor package communicating with a memory chip via a switch and a "Protocol Converter," illustrating the shift from parallel to serial communication pathways US 8,234,483 B2, Fig. 2C
  • Technical Importance: This approach sought to resolve the processor-memory bottleneck by leveraging the advancements and high data rates of serial, packet-based protocols that had become standard in networking and I/O communications US 8,234,483 B2, col. 4:51-64

Key Claims at a Glance

  • The complaint alleges infringement of "exemplary claims" but does not specify them in the body of the complaint Compl. ¶11 Claim 1 is the first independent claim of the '483 Patent.
  • The essential elements of independent claim 1 include:
    • An apparatus with at least one memory device.
    • At least one packet processor that is uniquely associated with the memory device.
    • The packet processor is adapted to provide read/write access to the memory device via a high-speed packet-switched serial interface.
    • This is accomplished by decapsulating information from a received packet and encapsulating responsive data into another packet for transmission.
    • The memory device and the packet processor are co-located on a single semiconductor die package that has an external port for the serial interface.
  • The complaint does not explicitly reserve the right to assert dependent claims.

III. The Accused Instrumentality

Product Identification

The complaint refers to the accused products as the "Exemplary Defendant Products" and states they are identified in charts attached as Exhibit 2 Compl. ¶11 As Exhibit 2 was not provided with the complaint, the specific accused products are not identified in the available document. The defendant is Super Micro Computer, Inc., a company known for producing servers and computing components.

Functionality and Market Context

The complaint alleges that the accused products "practice the technology claimed by the '483 Patent" Compl. ¶16 It asserts that these products are made, used, sold, and imported by the defendant Compl. ¶11 The complaint does not provide further technical details on the functionality or market position of the accused products.

IV. Analysis of Infringement Allegations

The complaint incorporates by reference claim charts from an external Exhibit 2, which is not included in the provided filing Compl. ¶16 Compl. ¶17 The narrative alleges that these charts demonstrate how the "Exemplary Defendant Products" satisfy all elements of the asserted claims Compl. ¶16 Without the charts, a detailed element-by-element analysis is not possible. The core of the infringement theory is that the defendant's products contain a computing architecture that infringes one or more claims of the '483 Patent Compl. ¶11

No probative visual evidence provided in complaint.

  • Identified Points of Contention:
    • Architectural Question: A central issue may be whether the defendant's products feature a "packet processor" and a "memory device" that are "co-located on a semiconductor die package" as required by claim 1. The physical arrangement and integration level of the components in the accused systems will be critical.
    • Functional Question: The analysis may turn on whether a component in the accused products performs the specific claimed functions of "decapsulating" memory commands from a serial packet and "encapsulating" the response. The court may need to determine if the functionality of the accused component matches the patent's description of a "packet processor."
    • Scope Question: A potential dispute may arise over whether standard server interconnect technologies used in the accused products fall within the scope of the claimed "high-speed packet switched serial interface," as defined by the patent.

V. Key Claim Terms for Construction

  • The Term: "packet processor"

  • Context and Importance: This term defines the core infringing component. Its construction will be critical for determining whether any part of the accused products' architecture performs the functions required by the claims. Practitioners may focus on this term because its scope dictates whether a general-purpose interconnect controller, for example, can be considered a "packet processor."

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The specification suggests this component can be part of a larger "bridge-architecture" US 8,234,483 B2, col. 8:14-16 and can be implemented as a programmable "bitstream processor" US 8,234,483 B2, col. 8:62-64, which may support an interpretation that covers a range of hardware that bridges communication protocols.
    • Evidence for a Narrower Interpretation: The abstract links the "protocol processor" to a "gigabit Ethernet interface" US 8,234,483 B2, abstract Furthermore, claim 1 requires it to be "uniquely associated" with a memory device, which could be argued to require a dedicated, rather than a general-purpose, functional unit US 8,234,483 B2, col. 11:29-30

  • The Term: "co-located on a semiconductor die package"

  • Context and Importance: This limitation defines the required physical relationship between the "packet processor" and the "memory device." Infringement hinges on whether the accused products meet this specific structural requirement.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: A party might argue that "semiconductor die package" could encompass multi-chip modules (MCMs) or other advanced packaging where multiple dies are integrated into a single functional package, not just a single monolithic piece of silicon.
    • Evidence for a Narrower Interpretation: The use of the singular "a semiconductor die package" in claim 1 suggests a single, discrete package contains both the memory and the processor US 8,234,483 B2, col. 11:46-48 Figures in the patent, such as Figure 5B, distinguish between a "Processor Chip Package" (55) and a "Mmeory [sic] Chip Package" (70) as separate entities, which could be used to argue that "co-located" requires integration beyond what is shown in that particular embodiment, but within a single package as claimed.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges induced infringement, stating that the defendant provides "product literature and website materials" that direct and encourage end users to operate the accused products in a manner that infringes the '483 Patent Compl. ¶14 Compl. ¶15
  • Willful Infringement: The basis for willfulness is alleged post-suit knowledge. The complaint asserts that the service of the "Original Complaint" provided the defendant with "actual knowledge of infringement," and that the defendant's continued infringing activities thereafter are willful Compl. ¶13 Compl. ¶14 The plaintiff also requests that the case be declared "exceptional" under 35 U.S.C. § 285 Compl. ¶E.i

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central issue will be one of physical architecture: Can the plaintiff demonstrate that the accused products contain a "memory device" and a "packet processor" that are "co-located on a semiconductor die package," as strictly required by claim 1, or does the defendant’s architecture physically separate these components in a way that avoids infringement?
  • A key question of claim construction will be the functional scope of "packet processor": Does this term, in the context of the patent, read on standard components within modern server architectures, or is it limited to a more specialized, dedicated processor for protocol conversion as described in the patent's specific embodiments?
  • An evidentiary challenge will be mapping the accused products to the claims: As the complaint lacks specific product details and relies on an unattached exhibit, a primary hurdle for the plaintiff will be to produce evidence showing that the defendant’s products not only use a serial interface for memory access but do so in the specific manner claimed by the '483 patent, including the unique association and co-location of the key components.