Monolithic 3DTM Inc v. Corsair Gaming Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Monolithic 3D™ Inc. (Texas)
  • Defendant: Corsair Gaming, Inc., Corsair Components, Inc., and Corsair Memory Inc. (Delaware)
  • Plaintiff's Counsel: Bayard, PA.; Fabricant, Rubino & Lambrianakos LLP
• Case Identification: 1:26-cv-00547, D. Del., 05/11/2026
• Venue Allegations: Venue is alleged to be proper in the District of Delaware because the Corsair Defendants are incorporated under the laws of the State of Delaware.
• Core Dispute: Plaintiff alleges that Defendant's solid-state drives (SSDs) which incorporate 3D NAND flash memory chips infringe five patents related to the structure and manufacturing methods of 3D semiconductor devices.
• Technical Context: The technology at issue is three-dimensional NAND (3D NAND) flash memory, a method of stacking memory cells vertically to achieve higher storage density than traditional planar (2D) NAND.
• Key Procedural History: The complaint alleges that Defendant had knowledge of the asserted patents and their infringement at least as of November 26, 2025, due to prior litigations involving the same accused memory components, specifically Monolithic 3D Inc v. Kioxia Corp, In the Matter of Certain NAND and DRAM Memory Chips (USITC), and an earlier case against Corsair. These allegations form the basis for the claim of willful infringement.

Case Timeline

Date	Event
2014-01-28	Earliest Priority Date ('330 & '961 Patents)
2015-09-21	Earliest Priority Date ('830 Patent)
2015-11-21	Earliest Priority Date ('006 Patent)
2018-03-06	Earliest Priority Date ('734 Patent)
2020-05-01	Accused Corsair MP700 Elite Product Launch
2025-03-11	'830 Patent Issued
2025-07-15	'330 Patent Issued
2025-08-26	'961 Patent Issued
2025-11-04	'734 Patent Issued
2025-11-26	Alleged Date of Notice via Prior Litigations
2026-02-24	'006 Patent Issued
2026-05-11	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 12,564,006 - "3D Semiconductor Device and Structure with Memory Cells and Multiple Metal Layers" (issued Feb. 24, 2026)

The Invention Explained

The complaint does not include a copy of the '006 patent for analysis. The description of the patented solution is based on the claim language recited in the complaint.

• Problem Addressed: As semiconductor device scaling in two dimensions has slowed, increasing memory capacity and performance has become a significant challenge for the industry '830 Patent, col. 1:20-24
• The Patented Solution: The invention, as embodied in the asserted claims, addresses this problem by creating a three-dimensional semiconductor device with multiple vertically stacked levels Compl. ¶25 The structure places memory control circuits on a "first level" and arranges memory cells in arrays on upper levels (e.g., "second level" and "fourth level"), enabling higher density by building upwards Compl. ¶25 Vertical connections are made using vias and/or thru-layer vias to link the different levels Compl. ¶25
• Technical Importance: This monolithic 3D architecture allows for a paradigm shift in semiconductor design, moving from planar to vertical scaling to increase device density and performance Compl. ¶15

Key Claims at a Glance

The complaint asserts at least Claim 1 Compl. ¶25

• A 3D semiconductor device comprising:
• A first level with first transistors comprising a single crystal channel.
• Multiple metal layers and a second, third, and fourth level of transistors stacked sequentially above the first level.
• The second and fourth levels comprising pluralities of memory cells.
• The first level comprising memory control circuits.
• The second memory cells comprising at least four independently controlled memory arrays.
• Each level comprising a dielectric electrical isolation layer and vias for vertical connection.
• At least one of the second transistors comprising a metal gate.

U.S. Patent No. 12,464,734 - "Method for Producing 3D Semiconductor Devices and Structures with Transistors and Memory Cells" (issued Nov. 4, 2025)

The Invention Explained

The complaint does not include a copy of the '734 patent for analysis. The description of the patented solution is based on the claim language recited in the complaint.

• Problem Addressed: The technical challenge lies in fabricating complex, multi-layered 3D semiconductor devices in a practical and scalable manner '830 Patent, col. 1:20-24
• The Patented Solution: The invention claims a method for producing a 3D device. The process involves providing a "first level" containing memory control circuits, forming at least a "second level" and a "third level" above it, and then performing processing steps (like etching) to create memory cells within these upper levels Compl. ¶45 A key step is "performing bonding of said first level to said second level," which suggests a fabrication technique where the control circuitry and memory arrays are built separately and then joined together Compl. ¶45
• Technical Importance: This manufacturing method enables the integration of logic and memory in a vertical stack, a key process for creating high-density 3D integrated circuits like 3D NAND flash Compl. ¶17

Key Claims at a Glance

The complaint asserts at least Claim 1 Compl. ¶45

• A method for producing a 3D semiconductor device comprising the steps of:
• Providing a first level comprising a first single crystal layer.
• Forming memory control circuits on the first level, which comprise single crystal transistors and at least two interconnection metal layers.
• Forming at least one second level and performing a first etch step into it.
• Forming at least one third level.
• Performing additional processing steps to form a plurality of first memory cells in the second level and second memory cells in the third level.
• Performing bonding of the first level to the second level, wherein the third level is disposed above the second level.
• The first level comprising control of power delivery to at least one third transistor.

U.S. Patent No. 12,362,330 - "3D Semiconductor Device and Structure with Connection Paths"

• Issued: July 15, 2025 Compl. ¶10
• Technology Synopsis: This patent describes a 3D semiconductor device constructed with multiple levels of transistors. The invention focuses on the "plurality of connection paths" that provide electrical connections between transistors on different levels, such as from a "first level" to a "third level" '330 Patent, abstract The first level is also described as containing at least one voltage regulator '330 Patent, abstract
• Asserted Claims: At least Claim 1 Compl. ¶65
• Accused Features: The complaint alleges that the vertically stacked architecture of the KIOXIA memory, including its various layers of transistors and interconnections, infringes the '330 patent Compl. ¶¶66-71

U.S. Patent No. 12,250,830 - "3D Semiconductor Memory Devices and Structures"

• Issued: March 11, 2025 Compl. ¶11
• Technology Synopsis: This patent discloses a 3D semiconductor device comprising a "first level" that includes both a single crystal layer and a memory control circuit. The invention specifies that the memory control circuit includes at least one "Look Up Table circuit ('LUT')" and that the overall device includes a "hybrid bonding layer" '830 Patent, abstract
• Asserted Claims: At least Claim 1 Compl. ¶82
• Accused Features: The complaint accuses the memory control circuit in the KIOXIA chip of containing an LUT for bad block management and utilizing a hybrid oxide-copper bonding layer to connect the memory array to the control layer Compl. ¶¶88-89

U.S. Patent No. 12,400,961 - "3D Semiconductor Device and Structure with Metal Layers"

• Issued: August 26, 2025 Compl. ¶12
• Technology Synopsis: This patent describes a multi-level semiconductor device with a specific arrangement of metal layers connecting transistors across different levels. Key features include the presence of at least one temperature sensor and a requirement that at least one element within the second level of transistors has been "processed independently" of the third level of transistors '961 Patent, abstract
• Asserted Claims: At least Claim 1 Compl. ¶99
• Accused Features: The complaint alleges the KIOXIA chip contains an on-chip temperature sensor and is manufactured using a process where memory tube etches for different decks (equated to claimed transistor levels) are performed separately, meeting the "processed independently" limitation Compl. ¶¶105-106

III. The Accused Instrumentality

Product Identification

The accused products are Corsair's storage devices incorporating 3D NAND flash memory, with the Corsair MP700 Elite SSD identified as an exemplary product Compl. ¶18 The core accused component within these SSDs is the KIOXIA BiCS8 3D TLC flash memory chip, model number T2BIGB5A2V Compl. ¶19

Functionality and Market Context

The Corsair MP700 Elite is a solid-state drive, a high-performance data storage device used in computers Compl. ¶18 Its functionality relies on the internal KIOXIA 3D NAND chip, which is a 218-layer vertically stacked flash memory Compl. ¶19 This 3D architecture allows for high storage capacity in a compact form factor. The complaint presents a photograph of the MP700 Elite SSD, highlighting the location of the KIOXIA memory chip on the circuit board Compl. ¶20

IV. Analysis of Infringement Allegations

The complaint does not provide copies of the '006 or '734 patents. The analysis below is based on the claim language recited in the complaint. The Patent Citation column is omitted as no specification is available for citation.

U.S. Patent No. 12,564,006 Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation
a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel	The accused product's NAND controller circuits (CMOS Bonded to Array or "CBA") are identified as the "first level," formed on a single crystal silicon substrate.	¶26
a first metal layer... a second metal layer overlaying said first metal layer	The accused product contains metal interconnect layers (M1, M2) within the first level.	¶34
a second level comprising a plurality of second transistors, said second level overlaying said first level	"3D NAND Deck 2" is identified as the "second level," containing a plurality of vertically arranged NAND flash memory cell transistors.	¶27
a third level comprising a plurality of third transistors, said third level overlaying said second level	A portion of "3D NAND Deck 1" is identified as the "third level," containing horizontally arranged memory cell transistors.	¶28
a fourth level comprising a plurality of fourth transistors, said fourth level overlaying said third level	A portion of "3D NAND Deck 1" is identified as the "fourth level."	¶29
said second level comprises a plurality of first memory cells, wherein each of said plurality of first memory cells comprises at least one of said second transistors	The NAND memory structure in "3D NAND Deck 2" is composed of memory cells, each comprising one transistor.	¶30
said first level comprises memory control circuits	The CMOS bonded to array (CBA) circuits in the "first level" provide access to the 3D NAND array for writing and reading values.	¶32
second memory cells comprise at least four memory arrays, wherein each of said four memory arrays are independently controlled	The 3D NAND die is split into four independent, independently controlled array sections. A top-down die photograph illustrates these four distinct array sections Compl. ¶33	¶33
at least one of said second transistors comprises a metal gate	The wordlines of the 3D NAND, which act as transistor gates, are composed primarily of tungsten, a metal.	¶35

U.S. Patent No. 12,464,734 Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation
providing a first level, said first level comprising a first single crystal layer; forming memory control circuits in and/or on said first level	The method of making the accused product provides a "first level" (the CMOS control circuitry) on a single crystal layer.	¶46
said memory control circuits comprise first single crystal transistors, and wherein said memory control circuits comprise at least two interconnection metal layers	The memory control circuits are alleged to be made with single crystal transistors and at least two metal layers for interconnection.	¶47
forming at least one second level; performing a first etch step into said at least one second level	The manufacturing process forms "3D NAND Deck 2" (the second level), and a "first etch step" is performed to define the memory tubes. A cross-section SEM image shows the result of this etch step Compl. ¶48	¶47; ¶48
forming at least one third level	The process forms "3D NAND Deck 1" (the third level) on top of the second level.	¶49
performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level	The process uses steps like lithography, deposition, and etch to form the memory cells within each NAND deck. A diagram illustrates the sequence of steps used to form the memory tube layers Compl. ¶50	¶50
wherein said at least one second transistor comprises a metal gate	The wordlines, which function as gate electrodes for the transistors, are made primarily of tungsten.	¶53
performing bonding of said first level to said second level	The manufacturing process involves bonding the CMOS control layer (first level) to the 3D NAND array (second level). A cross-section SEM image shows the bonding interface Compl. ¶54	¶54
said first level comprises control of power delivery to said at least one third transistor	The memory control circuits in the first level provide the necessary voltages to the entire 3D NAND stack, including transistors in the third level.	¶56

Identified Points of Contention

• Architectural Mapping: A likely point of dispute will be whether the physical structures of the accused KIOXIA chip, such as the "CMOS Bonded to Array" and "3D NAND Deck 1" and "Deck 2," map directly onto the patent's claimed "first level," "second level," "third level," etc. The defense may argue that the actual structure does not correspond to the specific layered arrangement required by the claims.
• Process Reconstruction: For the '734 method patent, infringement depends on reconstructing the process KIOXIA used to manufacture the chip. A central question will be whether Corsair can demonstrate, likely through discovery and expert analysis, that the manufacturing method meets every claimed step, including the specific characterization of "bonding" the first level to the second.

V. Key Claim Terms for Construction

The complaint does not provide the specifications of the '006 and '734 patents, precluding an analysis of intrinsic evidence for claim construction for those patents. The analysis for the '830 patent is provided below.

• The Term: "hybrid bonding layer" (from '830 Patent, Claim 1)
• Context and Importance: This term is critical because the infringement allegation hinges on the specific bonding technology used to connect the CMOS control layer to the 3D NAND memory array Compl. ¶89 The definition of "hybrid bonding" will determine whether the accused product's mixture of oxide and copper bonding falls within the claim's scope. Practitioners may focus on this term because the complaint's visual evidence explicitly points to a "mix of oxide and copper bonding" as the basis for infringement Compl. ¶89
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification does not appear to limit "hybrid bonding" to a single specific combination of materials. The general description of stacking layers suggests that any bonding technique that combines different material types (e.g., dielectric-to-dielectric and metal-to-metal) in the same interface could be considered "hybrid."
  • Evidence for a Narrower Interpretation: The patent does not provide an explicit definition of the term. A defendant may argue that the term should be limited to the specific embodiments or examples described, or that it has a particular, more limited meaning in the art that does not cover the specific oxide-copper combination used in the accused product.

VI. Other Allegations

• Indirect Infringement: The complaint alleges both induced and contributory infringement for all five patents-in-suit (Compl. ¶36; Compl. ¶37; Compl. ¶38). The allegations for inducement are based on Corsair's affirmative acts of providing instructions, product manuals, marketing materials, and other documentation that allegedly encourage and instruct customers and end-users to use the accused SSDs in an infringing manner Compl. ¶37
• Willful Infringement: The complaint alleges that Corsair's infringement has been and continues to be willful for all asserted patents Compl. ¶39 Compl. ¶59 Compl. ¶75 Compl. ¶93 Compl. ¶110 The basis for this allegation is pre-suit knowledge of the patents and infringement, allegedly obtained from prior litigations involving the same KIOXIA memory components, with notice alleged as of at least November 26, 2025 Compl. ¶39

VII. Analyst's Conclusion: Key Questions for the Case

• A central technical question will be one of architectural mapping: Does the physical structure of the accused KIOXIA BiCS8 chip, with its "CMOS Bonded to Array" and stacked "3D NAND Decks," correspond to the claimed sequence of "levels," "layers," and "transistors" as defined in the asserted patents? The case may turn on expert testimony dissecting the chip's construction and comparing it to the patent claims.
• A key legal question will be one of pre-suit knowledge: Did the prior litigations cited in the complaint, which involved the same third-party memory component, provide Corsair with sufficient knowledge of infringement to support a finding of willfulness? The outcome could significantly impact potential damages.
• An evidentiary question for the method patent ('734 patent) will be one of process reconstruction: Can the plaintiff obtain sufficient evidence through discovery to prove that the proprietary manufacturing process used by KIOXIA practices every step of the asserted method claim, particularly regarding the "bonding" of the control circuitry to the memory array?