Netlist Inc v. Micron Technology Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Netlist, Inc. (Delaware)
  • Defendant: Micron Technology, Inc. (Delaware); Micron Semiconductor Products, Inc. (Idaho); Micron Technology Texas LLC (Idaho); Avnet, Inc. (New York)
  • Plaintiff's Counsel: McKool Smith, P.C.
• Case Identification: 2:25-cv-00362, E.D. Tex., 07/28/2025
• Venue Allegations: Venue is alleged based on Defendants maintaining regular and established places of business within the Eastern District of Texas, specifically in Allen and Richardson, Texas, and having committed acts of patent infringement within the district.
• Core Dispute: Plaintiff alleges that Defendant's DDR5 dual in-line memory modules (DIMMs) infringe a patent related to on-module power management architectures.
• Technical Context: The lawsuit concerns DDR5 memory, the current industry standard for high-performance computing, where moving power management functions onto the memory module itself is a key technological shift enabling higher data rates and densities.
• Key Procedural History: The complaint notes a history of litigation between the parties, including what Netlist characterizes as a series of "retaliatory suits" filed by Micron in Idaho. The complaint also highlights prior, unrelated jury verdicts where Netlist was awarded significant damages against Samsung and Micron for infringement of other patents, which Netlist presents as evidence of its history of innovation.

Case Timeline

Date	Event
2007-06-01	Earliest Priority Date for '366 Patent
2025-07-28	Complaint Filed
2025-07-29	U.S. Patent No. 12,373,366 Issues

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 12,373,366 - "Memory with On-Module Power Management"

• Patent Identification: U.S. Patent No. 12,373,366, "Memory with On-Module Power Management," issued July 29, 2025 (the "'366 Patent").

The Invention Explained

• Problem Addressed: The patent's background describes the performance bottleneck in computer systems caused by the CPU having to manage data transfers between relatively slow main storage (like SSDs/HDs) and faster system memory (DRAM) '366 Patent, col. 1:41-62 Prior art attempts to place storage on a memory module form factor suffered from performance disparities between read and write operations '366 Patent, col. 2:31-40
• The Patented Solution: The invention describes a memory module, such as a DIMM, that integrates on-module power management circuitry, including multiple voltage converters and a voltage monitor '366 Patent, abstract This allows the module to manage its own power needs, receiving a single input voltage from the system board and generating the various regulated voltages required by its components (e.g., DRAM, controller) internally. An on-module controller monitors the input voltage and can trigger operations, such as writing data to nonvolatile memory if the voltage exceeds a threshold, providing a self-contained power management and data integrity solution '366 Patent, col. 25:21-39
• Technical Importance: Moving power management from the motherboard onto the memory module itself was a critical step in the evolution to the DDR5 standard, as it allows for more precise voltage control needed for higher data rates and improved power efficiency Compl. ¶32

Key Claims at a Glance

• The complaint asserts infringement of at least one claim, with the infringement analysis focused on independent Claim 1 Compl. ¶34 Compl. ¶¶36-78
• The essential elements of Claim 1 include:
  • A dual in-line memory module (DIMM) configured to fit into a system board's memory slot.
  • A printed circuit board (PCB) with edge connections for power, data, and address/control, which receives power from the system board as its only source of power.
  • A controller with a voltage monitor circuit and nonvolatile memory.
  • The voltage monitor is configured to: (i) monitor an input voltage, (ii) generate a trigger signal if the voltage exceeds a threshold, and (iii) transmit the signal to have the controller write data to the nonvolatile memory.
  • A set of DDR SDRAM memory devices.
  • First, second, third, and fourth converter circuits to receive power from an input voltage line and deliver four regulated voltage lines to various components.
  • A specific arrangement of at least two groups of DDR SDRAM devices on separate chip select lines, configured for independent channel operation with at least 72 total data conduits.
• The complaint alleges infringement of "at least one claim of the '366 Patent," implicitly reserving the right to assert other claims Compl. ¶34

III. The Accused Instrumentality

Product Identification

• The Accused Instrumentalities are Micron's DDR5 memory products, including but not limited to DDR5 RDIMMs (Registered DIMMs) and MRDIMMs (Multiplexer Rank DIMMs), and other products with similar structures Compl. ¶29

Functionality and Market Context

• The complaint alleges the accused products are DDR5 memory modules designed for servers in data-intensive applications like cloud computing and artificial intelligence Compl. ¶22 Compl. ¶27
• A key feature of DDR5, and the accused products, is the integration of power management onto the module itself via a Power Management Integrated Circuit (PMIC) Compl. ¶32
• The complaint further alleges that the accused DDR5 modules feature two independent 40-bit channels (32 data bits plus 8 ECC bits), which improves concurrency and performance over the prior DDR4 generation (Compl. ¶31).

IV. Analysis of Infringement Allegations

The complaint provides a narrative infringement theory for Claim 1. The diagram from a Micron technical brief, referenced in the complaint, shows the on-module PMIC as a central component receiving input voltage and distributing power to two independent memory subchannels Compl. p. 19 Another diagram referenced in the complaint provides a functional block diagram illustrating how the two independent channels (Channel A and Channel B) are organized with separate chip selects routed through a central Registering Clock Driver (RCD) Compl. p. 24

'366 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a printed circuit board (PCB) having edge connections configured to fit into the memory slot connector of the system board...wherein the power delivered to the DIMM from the power rails of the system board is the only power received by the DIMM;	The accused Micron DDR5 RDIMM comprises a PCB with "gold fingers" that fit into a motherboard's memory slot. The complaint alleges the DIMM's power supply is delivered from the system board power rails to the on-module PMIC and is the only power it receives.	¶39; ¶41	col. 38:52-60
a controller including a voltage monitor circuit and nonvolatile memory...the voltage monitor circuit configured to: (i) monitor an input voltage... (ii) generate a trigger signal... (iii) transmit the trigger signal...wherein the controller is configured to...write data into the nonvolatile memory...	The accused Micron DDR5 RDIMM comprises a PMIC, which serves as the controller. The PMIC allegedly includes a voltage monitor circuit to detect overvoltage conditions and nonvolatile memory. It is alleged to transmit a trigger signal to write status data to internal registers upon detecting an overvoltage event.	¶49; ¶¶51-55	col. 25:21-39
first, second, third, and fourth converter circuits coupled to the PCB...and configured to...deliver power via first, second, third, and fourth regulated voltage lines...	The PMIC on the accused DDR5 RDIMM is alleged to comprise circuitry that makes up four converter circuits. These converters receive input voltage from the system board and deliver multiple regulated voltages (e.g., VDDIO, VDD, VPP) to components on the module.	¶59; ¶¶61-67	col. 28:34-44
wherein the plurality of DDR SDRAM devices includes: a first group of at least five DDR SDRAM devices that are each connected to a first chip select line...a second group of at least four DDR SDRAM devices that are each connected to a second chip select line...	The accused 80-bit DDR5 RDIMM module is alleged to include two independent channels (Channel A and Channel B), each containing at least five SDRAM devices connected to a separate chip select signal group.	¶70; ¶72	col. 41:45-50
wherein when power from the power rails of the system board is provided...the first group of DDR SDRAM devices is configured to be enabled...to receive or output at least 40 1-bit DDR data signals in parallel...independently of whether the second group...is enabled...	The accused DDR5 RDIMM includes an RCD that receives independent read/write commands for either Channel A or Channel B. This enables each 40-bit channel to receive or output data independently of the other channel's operation.	¶74	col. 34:1-13

• Identified Points of Contention:
  • Scope Questions: Claim 1 requires that power from the system board be "the only power received by the DIMM." A potential point of contention is whether this language can be read to exclude any other power-carrying signals on the connector, such as low-power management bus signals, which could be present in a standard DDR5 interface. The absolute nature of the term "only" suggests this could be a focal point for a non-infringement argument.
  • Technical Questions: The complaint maps the claimed "controller" to the accused product's PMIC Compl. ¶49 A key question will be whether the PMIC's alleged function of logging an overvoltage event by "writing binary code into real time status registers" Compl. ¶55 meets the claim limitation of performing a "write operation to write data into the nonvolatile memory." The dispute may center on whether writing to a status register constitutes writing to "nonvolatile memory" for the purposes of data preservation as contemplated by the patent.

V. Key Claim Terms for Construction

• The Term: "controller"

• Context and Importance: The complaint alleges the accused product's PMIC is the claimed "controller" Compl. ¶49 The definition of this term is critical, as the PMIC is a standard component in DDR5 modules. Practitioners may focus on this term because if "controller" is construed narrowly to mean a more complex device with data management duties (as depicted in Figure 7 of the '366 Patent), it may not read on a standard PMIC, which primarily manages power regulation.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patent abstract describes a "controller including a voltage monitor circuit and nonvolatile memory," a function the complaint alleges the PMIC performs '366 Patent, abstract This could support an interpretation where any on-module component performing the claimed monitoring and triggering functions qualifies as the "controller."
  • Evidence for a Narrower Interpretation: The patent's detailed description and figures describe the on-module controller ("CDC 502") as performing extensive functions beyond power monitoring, including command interpretation, scheduling, and address mapping '366 Patent, Fig. 7 '366 Patent, col. 15:7-49 A defendant may argue this context limits the term "controller" to a device with these broader data and command management responsibilities, not just a PMIC.

• The Term: "wherein the power delivered to the DIMM from the power rails of the system board is the only power received by the DIMM"

• Context and Importance: This limitation appears in claim element [1a] and presents a potentially strict requirement. Its interpretation will be central to determining infringement, as standard memory interfaces can contain multiple voltage and signaling pins.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patent's abstract states the module couples to a host for "provision of power, data, address and control signals" '366 Patent, abstract A plaintiff might argue that "only power" should be interpreted in this context to mean the main operating power, distinguishing it from low-power "control signals" that are not used to operate the primary memory functions.
  • Evidence for a Narrower Interpretation: The plain language of the claim is absolute. A defendant could argue that any other electrical power source provided through the connector, regardless of its purpose (e.g., for standby logic, management bus interface), would fall outside the scope of "only power." The specification does not appear to explicitly define or limit what constitutes "power," leaving the term open to a strict, literal interpretation.

VI. Other Allegations

• Indirect Infringement: The complaint alleges Defendants induce infringement by providing customers with "specifications, datasheets, instruction manuals, and/or other materials that encourage and facilitate infringing uses" of the accused products Compl. ¶79 It is also alleged that Defendants contribute to infringement because the accused products are a material part of the invention and have no substantial noninfringing uses Compl. ¶80
• Willful Infringement: Willfulness is alleged based on Defendants having notice of the '366 Patent "since at least the filing of this Complaint" Compl. ¶81 Compl. ¶82 The allegation is based on post-suit knowledge.

VII. Analyst's Conclusion: Key Questions for the Case

The resolution of this case may depend on the court's determination of several key questions:

• A core issue will be one of definitional scope: can the term "controller," which the patent describes as a component with extensive data and command management functions, be construed to read on a standard Power Management Integrated Circuit (PMIC) whose primary role is power regulation?

• A second central question will be one of claim scope and factual compliance: does the absolute limitation that the module receives power only from the system board's power rails read on a standard DDR5 DIMM, which may receive other electrical inputs through the connector? The case may turn on evidence regarding the precise electrical nature of the accused DIMM interface.

• A key evidentiary question will be one of functional mapping: does the accused PMIC's alleged function of writing an overvoltage event to a status register constitute the claimed sequence of a "trigger signal" causing a "write operation to write data into the nonvolatile memory," or is there a fundamental mismatch in the technical purpose and operation?