Netlist Inc v. Micron Technology Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Netlist, Inc. (Delaware)
  • Defendant: Micron Technology, Inc.; Micron Semiconductor Products, Inc.; Micron Technology Texas LLC (Delaware and Idaho)
  • Plaintiff's Counsel: McKool Smith, P.C.; Irell & Manella LLP
• Case Identification: 1:26-cv-00246, E.D. Tex., 05/19/2025
• Venue Allegations: Plaintiff alleges venue is proper because Defendants commit acts of patent infringement in the district and maintain regular and established places of business in the district, specifically citing an office at 805 Central Expressway South, Suite 100, Allen, Texas.
• Core Dispute: Plaintiff alleges that Defendant's High-Bandwidth Memory (HBM) products infringe a patent related to the architecture of stacked memory dies and the management of electrical loads on their interconnects.
• Technical Context: The dispute centers on High-Bandwidth Memory (HBM), a key enabling technology for high-performance computing and artificial intelligence applications that relies on stacking multiple memory dies vertically to achieve high data throughput and power efficiency.
• Key Procedural History: The complaint was filed one day before the patent-in-suit was scheduled to issue. Plaintiff alleges this action is preemptive, anticipating a "retaliatory suit" from Micron in Idaho, and seeks a declaration that this suit was not brought in bad faith. The complaint also references a history of litigation between the parties and with other major memory manufacturers, including jury verdicts in favor of the Plaintiff.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 12,308,087 - "Memory Package Having Stacked Array Dies and Reduced Driver Load"

The patent-in-suit is U.S. Patent No. 12,308,087, issued May 20, 2025 (the "'087 Patent").

The Invention Explained

• Problem Addressed: In memory packages with vertically stacked semiconductor dies, a single driver must transmit signals to all dies through a shared interconnect. This creates a significant electrical load, requiring a large and power-hungry driver, which consumes valuable space and energy on the control die '087 Patent, col. 1:25-34
• The Patented Solution: The invention proposes partitioning the stack of memory dies into multiple subsets and using separate, distinct interconnects to communicate with each subset. By dividing the signal path, the electrical load on any single driver is reduced, allowing for the use of smaller, more efficient drivers '087 Patent, abstract '087 Patent, col. 4:5-15 The architecture uses a control die to manage these partitioned signal paths to different groups of stacked DRAM dies '087 Patent, Fig. 2
• Technical Importance: This load-reduction technique is intended to improve performance and power efficiency in high-density, stacked-die memory architectures, which are critical for meeting the demands of modern data-intensive applications '087 Patent, col. 1:35-44

Key Claims at a Glance

• The complaint asserts at least independent claim 1 Compl. ¶27
• Essential elements of claim 1 include:
  • A DRAM package with stacked DRAM dies comprising at least a first and a second plurality of dies.
  • Die interconnects, including through-silicon vias (TSVs), to conduct signals to and from the DRAM dies.
  • A control die coupled between external terminals and the stacked DRAM dies.
  • A first command/address (C/A) interconnect in electrical communication with the first plurality of DRAM dies but not with the second plurality.
  • A second C/A interconnect in electrical communication with the second plurality of DRAM dies but not with the first plurality.
  • First and second unidirectional interconnects for conducting signals to and from the control die, respectively.
  • A control die configured to receive read signals via the first unidirectional interconnects and drive write signals via the second unidirectional interconnects.
• The complaint does not explicitly reserve the right to assert dependent claims.

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are Micron's High-Bandwidth Memory products, including any Micron HBM3E, and newer products such as HBM4 and HBM4e (collectively, the "Accused HBM Products") Compl. ¶24

Functionality and Market Context

• The Accused HBM Products are described as high-speed memory technology that utilizes vertically stacked memory dies to achieve high bandwidth and lower power consumption Compl. ¶23
• The complaint alleges these products feature a stack of memory dies (e.g., 8, 12, or 16 dies) on top of a base logic die, with communication occurring through through-silicon vias (TSVs) that pass vertically through the stack Compl. ¶28 An image from Micron's website shows a "12-high" HBM3E cube mounted next to a GPU, illustrating its intended use Compl. p. 10
• Plaintiff alleges these products are critical for generative AI innovation and are used in servers for cloud computing and other data-intensive applications Compl. ¶22 Compl. ¶23 The complaint also asserts that the Accused HBM Products are compliant with industry standards promulgated by the Joint Electron Device Engineering Council (JEDEC) Compl. ¶25

IV. Analysis of Infringement Allegations

'087 Patent Infringement Allegations

Identified Points of Contention

• Scope Questions: A central question may be whether the architecture defined by the JEDEC standard for HBM, which the accused products allegedly follow Compl. ¶25, is coextensive with the specific interconnect partitioning claimed in elements [1e], [1f], [1g], and [1h] of the '087 Patent. The defense may argue that standard-compliant HBM architecture does not practice the patent's specific requirement of electrically isolating C/A and data interconnects between different pluralities of dies.
• Technical Questions: The complaint alleges that some TSVs "appear to only electrically interconnect to some of the dies in the stack, while others may electrically bypass certain groups of dies" Compl. ¶33 This suggests a key factual dispute will be proving the actual internal wiring and signal paths within Micron's products and demonstrating that they match the claimed partitioning, an analysis that may require evidence beyond publicly available datasheets.

V. Key Claim Terms for Construction

The Term: "control die"

• Context and Importance: This term is central as it defines the component alleged to perform the patented load-management functions. The infringement analysis depends on whether Micron's "logic die" or "buffer die" Compl. ¶31 meets the full scope of this term as defined by the patent.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent claims a "control die coupled between the terminals and the stacked DRAM dies" that includes "conduits" for signals '087 Patent, cl. 1 This could be read broadly to cover any base logic die that manages I/O for a DRAM stack.
  • Evidence for a Narrower Interpretation: The specification describes the control die as containing specific drivers and responding to signals to send "appropriate control signals to the array dies" '087 Patent, col. 2:51-54 This language, along with the detailed logic described in claim 1 (e.g., elements [1j], [1m], [1n], [1o]), may support a narrower construction requiring the presence of specific control and logic capabilities beyond simple signal buffering.

The Term: "unidirectional interconnects"

• Context and Importance: The complaint maps this term directly to the "RDQS" (read) and "WDQS" (write) data strobes used in JEDEC-compliant HBM memory Compl. ¶35 The viability of the infringement claim for elements [1k] through [1o] hinges on whether these standard strobes function as the claimed "unidirectional interconnects."
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim language describes the interconnects functionally, as being "configured to conduct signals from" the DRAM dies to the control die, and vice-versa '087 Patent, cl. 1 This functional description may be broad enough to read on the functionally distinct read and write strobes of the HBM standard.
  • Evidence for a Narrower Interpretation: The patent distinguishes between "data interconnects" and "unidirectional interconnects" in the claims. A defendant may argue this implies a structural or functional difference not present in a standard HBM design, where read/write strobes are fundamentally part of the data-transfer mechanism.

VI. Other Allegations

Indirect Infringement

The complaint does not provide sufficient detail for analysis of indirect infringement. The allegations focus on direct infringement by "making, using, selling, offering to sell, and/or importing" the Accused HBM Products Compl. ¶27

Willful Infringement

The complaint seeks a finding of willful infringement Compl., Prayer D However, it does not plead any facts establishing that Micron had knowledge of the '087 Patent prior to the lawsuit. As the complaint was filed on May 19, 2025, and the '087 Patent issued on May 20, 2025, any allegation of willfulness could only be based on knowledge obtained on or after the date the suit was filed.

VII. Analyst's Conclusion: Key Questions for the Case

• A core issue will be one of claim scope versus industry standard: Does Micron's implementation of the JEDEC standard for HBM products meet the specific, partitioned interconnect architecture required by Claim 1 of the '087 Patent? The case will likely turn on whether adherence to the public standard is sufficient to prove infringement of the patent's detailed limitations.
• A second central question will be evidentiary: Beyond marketing materials and industry standards, what technical evidence can Plaintiff provide to demonstrate that the internal circuitry and signal paths of the Accused HBM Products function with the precise electrical isolation between die groupings as mandated by the patent claims?
• Finally, a key procedural question arises from the timing of the suit, which was filed the day before the patent issued. This raises the question of preemption and legal strategy: How will the court treat a patent infringement claim and a request for a finding of willfulness when the suit was filed before the patent rights formally came into existence, a strategy Plaintiff itself frames as a preemptive measure against anticipated litigation Compl. ¶2?