Samsung Electronics Co Ltd v. Netlist Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Samsung Electronics Co., Ltd. and its U.S. affiliates (Republic of Korea, California, New York)
  • Defendant: Netlist, Inc. (Delaware)
  • Plaintiff’s Counsel: Morris, Nichols, Arsht & Tunnell LLP
• Case Identification: 1:25-cv-01371, D. Del., 11/11/2025
• Venue Allegations: Venue is asserted as proper in the District of Delaware because Defendant Netlist, Inc. is a Delaware corporation and is therefore subject to personal jurisdiction in the district.
• Core Dispute: Plaintiff seeks a declaratory judgment that its DDR5 memory modules do not infringe Defendant’s U.S. Patent No. 9,824,035, which relates to timing control in high-density memory modules.
• Technical Context: The technology at issue involves the architecture of dual in-line memory modules (DIMMs), a critical component for performance in servers, data centers, and high-end computers.
• Key Procedural History: This declaratory judgment action arises from a protracted, multi-forum dispute following the purported 2020 termination of a 2015 patent license agreement between the parties. The complaint notes that Defendant has sued Plaintiff in the Eastern District of Texas and the International Trade Commission (ITC), alleging infringement of the patent-in-suit. Significantly, the complaint also notes that in a 2023 inter partes review (IPR) proceeding initiated by a third party, the Patent Trial and Appeal Board (PTAB) found the primary asserted claims of the patent-in-suit to be unpatentable. Plaintiff alternatively alleges Defendant has breached its contractual obligation to license the patent on reasonable and non-discriminatory (RAND) terms and that the patent is unenforceable due to inequitable conduct during prosecution.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,824,035 - Memory Module with Timing-Controlled Data Paths in Distributed Data Buffers

The Invention Explained

• Problem Addressed: In high-speed, high-density computer memory modules, signals traveling from a central controller to various memory chips can arrive at slightly different times due to "unbalanced wire lengths" and different electrical loads '971 Patent, col. 2:25-33 Compl. ¶68 As memory speeds increase, these timing variations, or "skew," can cause errors, and traditional compensation methods performed by the main system memory controller become insufficient '971 Patent, col. 2:25-33
• The Patented Solution: The patent describes a memory module architecture that distributes "buffer circuits" across the module board, placing them closer to the memory devices they serve '971 Patent, Abstract As depicted in the patent's Figure 2C, these buffers intercept signals and can locally adjust their timing '971 Patent, col. 4:6-17 The core inventive concept is that these buffer circuits contain logic configured to "obtain timing information" during one type of memory operation (e.g., a write operation) and then use that information to "control timing" of data and strobe signals during a subsequent, different memory operation (e.g., a read operation) '971 Patent, Abstract Compl. ¶69
• Technical Importance: This decentralized approach to timing management allows for the design of faster and denser memory modules by offloading complex signal timing responsibilities from the system's central memory controller to intelligent buffers located directly on the memory module itself Compl. ¶68

Key Claims at a Glance

• The complaint asserts non-infringement of independent claim 1, which the PTAB has since found unpatentable (Compl. ¶104, ¶106).
• The essential elements of independent claim 1 include:
  • A memory module with a module board, a module control device, memory devices, and a plurality of buffer circuits.
  • The module control device receives memory command signals and outputs module command and control signals.
  • The memory devices perform a "first memory operation" in response to the module command signals.
  • Each buffer circuit includes data paths and logic that is "further configured to obtain timing information based on one or more signals received by the each respective buffer circuit during a second memory operation prior to the first memory operation" and to use that timing information to control the timing of signals on the data paths.
• The complaint notes that claims 2-22 depend on claim 1 and are therefore also not infringed Compl. ¶107

III. The Accused Instrumentality

Product Identification

Samsung DDR5 multiplexed rank dual in-line memory modules (“MRDIMM”) and other DIMMs that comply with DDR5 or similar standards (Compl. ¶13, ¶64, ¶70).

Functionality and Market Context

The complaint describes the accused products as standard-compliant memory modules used in modern computer systems Compl. ¶64 The functionality relevant to the dispute involves timing calibration procedures, specifically "MDQS Receive Enable (MRE) and MDQS Read Delay (MRD) training" modes Compl. ¶106 The complaint alleges that these training modes are used to set timing information but are not "memory operations" as required by the patent's claims Compl. ¶106 These products represent a significant component of the high-performance computing market Compl. ¶73

IV. Analysis of Infringement Allegations

The complaint seeks a declaratory judgment of non-infringement. The analysis below summarizes the plaintiff's core non-infringement theory as presented against claim 1. The complaint includes a diagram, adapted from the '035 patent's Figure 2C, to illustrate the general architecture of a memory module with a central controller and distributed data buffers Compl. ¶67, p. 17 This figure provides context for the patented solution of embedding timing control logic within those distributed buffers.

• '035 Patent Infringement Allegations

• Identified Points of Contention:
  • Scope Questions: The central dispute appears to hinge on claim construction. A primary question for the court will be: Does the term "memory operation," as used in claim 1, encompass the specialized "MRE and MRD training" modes used by the accused Samsung products?
  • Technical Questions: A related technical question is whether the signals received during the accused training modes function as the claimed "second memory operation" for the purpose of "obtain[ing] timing information." The complaint raises the question of whether a process can be a "memory operation" if, as alleged, the primary data and strobe lines are not available for data transmission to or from the host controller during that process Compl. ¶106

V. Key Claim Terms for Construction

• The Term: "memory operation"
• Context and Importance: The definition of this term is dispositive for the non-infringement argument presented in the complaint. If "memory operation" is construed narrowly to include only standard data access functions (e.g., read, write), Samsung's argument that its timing "training" modes fall outside the claim scope may be strengthened. Conversely, a broader construction that includes any signaling event used to configure the memory subsystem could favor Netlist's infringement position. Practitioners may focus on this term because it creates a clear line of demarcation between the parties' technical arguments.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim language itself distinguishes between a "first memory operation" and a "second memory operation," which suggests the patent contemplates different types of operations '035 Patent, col. 20:43-45 The purpose of the "second memory operation" is specifically "to obtain timing information," which could be interpreted to include calibration or training functions whose primary purpose is establishing timing parameters rather than transferring user data.
  • Evidence for a Narrower Interpretation: The patent specification frequently discusses memory operations in the context of compensating for delays during "write and/or read operations" '035 Patent, col. 2:29 The detailed description of embodiments refers to memory operations such as "read, write, refresh, precharge, etc." '035 Patent, col. 3:28-33, potentially suggesting that the term was intended to cover these conventional memory access commands rather than distinct training modes.

VI. Other Allegations

In addition to its non-infringement count, the complaint pleads two alternative counts.

• Breach of Contract (RAND Obligations): Samsung alleges that, to the extent the '035 patent is deemed essential to JEDEC memory standards, Netlist is contractually bound by JEDEC's patent policy to offer a license on reasonable and non-discriminatory (RAND) terms Compl. ¶113 The complaint alleges Netlist breached this duty by, among other things, seeking an exclusion order at the ITC and making licensing demands that are inconsistent with RAND principles (Compl. ¶100, ¶119).
• Unenforceability due to Inequitable Conduct: The complaint alleges that inventors of the '035 patent attended JEDEC standards meetings where third parties (specifically Intel) presented the core technical concepts that were later claimed in the '035 patent Compl. ¶¶128-132 It is alleged that the inventors knew these presentations were material prior art but intentionally withheld them from the U.S. Patent and Trademark Office during prosecution with an intent to deceive the examiner, rendering the patent unenforceable (Compl. ¶136, ¶140).

No probative visual evidence provided in complaint.

The complaint does not contain allegations of indirect or willful infringement against Samsung, as Samsung is the plaintiff seeking a declaratory judgment of non-infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

This declaratory judgment action presents several fundamental questions for the court, all of which are significantly impacted by the existing PTAB decision finding the asserted claims unpatentable. Assuming the PTAB's decision is appealed and its outcome is uncertain, the case will likely turn on the following issues:

• A core issue will be one of definitional scope: Can the claim term "memory operation," which in the patent’s context often refers to read/write cycles, be construed to cover the specialized timing "training" modes implemented in the accused standard-compliant DDR5 memory modules?
• A critical question of fact will be one of prosecution conduct: Can Samsung present clear and convincing evidence that Netlist’s inventors learned of the claimed concepts from prior JEDEC presentations and intentionally withheld that material art from the Patent Office with deceptive intent, which would render the patent unenforceable?
• An alternative dispositive issue will be one of contractual commitment: To the extent the patent is found valid and infringed, is it essential to a JEDEC standard, and if so, did Netlist breach its binding RAND licensing obligations by pursuing an ITC exclusion order against a willing licensee?