Empire Technology Development LLC v. Advanced Micro Devices Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Empire Technology Development LLC (Delaware)
  • Defendant: Advanced Micro Devices, Inc. (Delaware)
  • Plaintiff's Counsel: Potter Anderson & Corroon LLP
• Case Identification: 1:25-cv-01049, D. Del., 03/12/2026
• Venue Allegations: Venue is asserted in the District of Delaware based on Defendant being a Delaware corporation and therefore a resident of the district.
• Core Dispute: Plaintiff alleges that Defendant's multicore processors featuring Zen 3 and later microarchitectures infringe two patents related to efficient on-chip message routing and power management based on leakage current variability.
• Technical Context: The technologies at issue address fundamental challenges in modern semiconductor design: improving inter-core communication speed and managing power consumption to enhance processor performance and efficiency.
• Key Procedural History: The currently operative First Amended Complaint was filed on March 12, 2026, following an original complaint filed on August 21, 2025. The complaint notes that application publications for both patents-in-suit were cited during the prosecution of patent applications filed by Intel Corporation, a competitor to the Defendant.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,367,370 - "NOC LOOPBACK ROUTING TABLES TO REDUCE I/O LOADING AND OFF-CHIP DELAYS" (issued June 14, 2016)

The Invention Explained

• Problem Addressed: The patent describes an inefficiency in multicore processors where messages between two processes running on different cores of the same chip are routed through an external, "off-chip" network. This process introduces "undesirable and unnecessary network delays and input/output loading at the hardware" '370 Patent, col. 3:26-33
• The Patented Solution: The invention proposes a "loopback simulator" at the processor's hardware layer that intercepts messages intended for another core on the same chip before they are sent to the external network '370 Patent, abstract To do this, it generates a "core-process-to-IP-address map" to determine if a message's destination is local '370 Patent, col. 4:56-65 If the destination is on the same chip, the simulator redirects the message internally via on-chip communication, avoiding the off-chip network entirely and thereby reducing latency '370 Patent, col. 4:43-57
• Technical Importance: In an era of increasing core counts and widespread virtualization, optimizing on-chip communication is critical for overall system performance, particularly in datacenters where many virtual machines may run on a single physical processor '370 Patent, col. 2:10-19

Key Claims at a Glance

• The complaint asserts independent claim 14 Compl. ¶24
• The essential elements of claim 14 are:
  • A multicore processor comprising a plurality of processor cores.
  • A controller configured to identify processes on the cores that are adapted to communicate via an off-chip network.
  • The controller is further configured to:
    • generate a core-process-to-IP-address map;
    • identify a destination processor core for a message using that map; and
    • identify the data to be delivered.
  • A "loopback simulator" at a processor hardware layer configured to deliver the message via on-chip communication by processing the data back into on-chip "flits" for the destination core.
• The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 9,671,850 - "LEAKAGE CURRENT VARIABILITY BASED POWER MANAGEMENT" (issued June 6, 2017)

The Invention Explained

• Problem Addressed: The patent explains that in modern processors, microscopic variations in the manufacturing process cause "leakage current variability," meaning different transistors and functional sub-units on a chip consume different amounts of power even when idle '850 Patent, col. 1:26-30 This variability makes it difficult to efficiently manage power consumption '850 Patent, col. 4:45-50
• The Patented Solution: The invention describes a method to create a "micro-architectural leakage map" for a processor core by analyzing data from power controllers and processor instruction counters '850 Patent, abstract This map provides a detailed profile of the leakage characteristics of the core's various sub-units. This profile then enables a power management application to make more intelligent decisions, such as deactivating particularly "leaky" sub-units and migrating processing threads to more power-efficient sub-units to compensate '850 Patent, col. 6:22-28 '850 Patent, abstract
• Technical Importance: As power consumption and heat dissipation became primary limiting factors in processor performance, managing power at a granular level based on actual, measured leakage characteristics provided a path to greater efficiency, longer battery life, and reduced operating costs '850 Patent, col. 3:51-54

Key Claims at a Glance

• The complaint asserts independent claim 12 Compl. ¶68
• The essential elements of method claim 12 are:
  • Receiving computation data from a power controller and processor instruction counters (PICs) of a core.
  • Generating a table of linear combination samples from that data, with each sample including a power usage value for a sub-unit of the core.
  • Generating a "micro-architectural leakage map" of the core from the samples in the table.
  • In response to deactivating a second sub-unit based on the map, directing a thread to a first sub-unit.
  • If the first sub-unit cannot compensate, reactivating the second sub-unit.
  • Executing a thread migration to move the thread to the second sub-unit.
  • Upon completion, moving the thread back to the first sub-unit and deactivating the second sub-unit.
• The complaint does not explicitly reserve the right to assert dependent claims for this patent.

III. The Accused Instrumentality

Product Identification

• The accused products are AMD multicore processors that include the Zen 3, Zen 3+, Zen 4, Zen 4c, Zen 5, and Zen 5c microarchitectures Compl. ¶24 Compl. ¶68 Specific product families named include the AMD Ryzen and AMD EPYC series processors Compl. ¶28 Compl. ¶71

Functionality and Market Context

• The complaint alleges that the accused processors infringe the '370 Patent through an architectural change introduced in Zen 3. This change unified up to eight processor cores into a single Core Complex (CCX) with a shared L3 cache, which allegedly allows for direct on-chip communication that previously required off-chip routing Compl. ¶¶56-57 This configuration is alleged to demonstrate the capability of loopback and inter-core messaging Compl. ¶59 A diagram in the complaint contrasts the Zen 2 layout with the unified Zen 3 layout to illustrate this architectural change Compl. p. 24
• For the '850 Patent, the complaint focuses on the "adaptive power management features" introduced in the Zen 3+ and later microarchitectures Compl. ¶79 These features are described as a "five-pronged approach" to power management that includes optimizations to the CPU microarchitecture with "fine-grained power-gating of individual cores" and firmware that interacts with the operating system to "understand the nature of the performance demand" Compl. ¶80 A marketing slide shows these features as "5 Layers of Power Optimization," including a "Core Architecture" layer where the "power of all design elements [is] optimized for better leakage" Compl. p. 35 Compl. p. 36

IV. Analysis of Infringement Allegations

'370 Patent Infringement Allegations

Identified Points of Contention

• Scope Questions: The analysis may turn on whether AMD's integrated fabric and shared L3 cache architecture can be construed as a "loopback simulator." The patent describes a distinct component that intercepts and redirects traffic at I/O ports '370 Patent, Fig. 3, which raises the question of whether a general-purpose, high-speed interconnect that provides a direct path between cores meets this limitation.
• Technical Questions: What evidence does the complaint provide that the accused products "generate a core-process-to-IP-address map" as required by the claim? The complaint alleges the controllers are "configured to" perform this function but focuses its technical evidence on the physical architecture of the shared L3 cache rather than on the existence or operation of such a map (Compl. ¶51; Compl. ¶52).

'850 Patent Infringement Allegations

Identified Points of Contention

• Technical Questions: Does the complaint provide sufficient evidence that AMD's power management system technically performs the specific, sequential method steps of claim 12, particularly the sequence of deactivation, attempted compensation by another sub-unit, reactivation, thread migration, and subsequent deactivation? The allegations point to general capabilities for power-gating and thread management but do not map them to this precise, conditional workflow Compl. ¶¶98-101
• Scope Questions: Can the term "micro-architectural leakage map," as generated from a "table of linear combination samples," be read to cover the general power telemetry gathered by AMD's SMU? The patent describes a specific mathematical derivation for this map '850 Patent, col. 5:1-13, raising the question of whether AMD's system performs a functionally equivalent process.

V. Key Claim Terms for Construction

• Patent: '370 Patent

• The Term: "loopback simulator"

• Context and Importance: This term is the central component of the asserted claim. The dispute may depend on whether this term is construed broadly to cover any hardware that keeps local traffic on-chip, or narrowly to require a specific module that intercepts and mimics off-chip routing.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patent summary describes the invention broadly as "generating a simulated network loopback at a processor hardware layer to deliver messages between the process(es) without using the off-chip network" '370 Patent, col. 2:30-33 This functional language may support an interpretation covering any hardware that achieves this result.
  • Evidence for a Narrower Interpretation: The detailed description and figures depict a "loopback controller 302" with a "loopback simulator 307" as a distinct block coupled to I/O ports '370 Patent, Fig. 3 The specification describes this simulator as potentially receiving packets, decoding them into flits, and placing them on the on-chip network, an active process of simulation rather than a passive, direct connection '370 Patent, col. 5:47-54

• Patent: '850 Patent

• The Term: "micro-architectural leakage map"

• Context and Importance: The generation of this "map" is the foundational step upon which the entire power management method of claim 12 rests. The infringement case requires demonstrating that AMD's processors create this specific data structure, not just a generic set of power telemetry.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patent's background discusses the general problem of leakage current variability '850 Patent, col. 1:26-30 This context could support a view that any data structure which characterizes this variability for power management purposes constitutes a "map."
  • Evidence for a Narrower Interpretation: Claim 12 explicitly requires the map to be generated "from the linear combination samples within the table," which are themselves generated from power controller and PIC data. The specification further details this process, suggesting the "map" is the specific output of this quasi-mathematical analysis, not just any collection of sensor data '850 Patent, col. 5:1-13

VI. Other Allegations

• Indirect Infringement: The complaint alleges inducement of infringement for both patents. It asserts that AMD provides customers and end-users with instructions, product manuals, datasheets, and marketing materials that instruct them to use the accused processors in an infringing manner Compl. ¶31 Compl. ¶74
• Willful Infringement: Willfulness is alleged for both patents based on AMD's purported knowledge of the patents since, at the latest, the date the original complaint in the action was filed and served on August 21, 2025 Compl. ¶30 Compl. ¶73

VII. Analyst's Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: can the term "loopback simulator," described in the '370 Patent in the context of a discrete controller that intercepts and redirects I/O traffic, be construed to cover a modern, unified processor architecture where a shared L3 cache and integrated fabric provide a direct, high-speed data path between cores?
• A key evidentiary question will be one of functional equivalence: does the complaint demonstrate that AMD's sophisticated, telemetry-driven power management system performs the specific, multi-step method recited in claim 12 of the '850 Patent, including the creation of a "micro-architectural leakage map" from specific data inputs and the precise, conditional sequence of sub-unit deactivation, reactivation, and thread migration?
• A central point of contention will likely be the level of abstraction: does infringement lie in the high-level functional results described in AMD's marketing materials (e.g., improved on-chip communication, leakage-aware power optimization), or does it require a more granular showing that the accused products implement the specific structures and methods detailed in the patent specifications and claims?