MYW Semitech LLC v. Apple Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: MYW Semitech, LLC (Delaware)
  • Defendant: Apple Inc. (California)
  • Plaintiff's Counsel: Stamoulis & Weinblatt LLC
• Case Identification: 1:25-cv-00504, D. Del., 07/07/2025
• Venue Allegations: Plaintiff alleges venue is proper in the District of Delaware because Defendant Apple Inc. has a regular and established place of business in the district, including a physical Apple Store, and has committed the alleged acts of infringement in the district.
• Core Dispute: Plaintiff alleges that numerous Apple products containing A-series and S-series processors, which utilize Integrated Fan-Out Package-on-Package (InFO PoP) technology, infringe three patents related to advanced semiconductor chip packaging.
• Technical Context: The technology at issue involves methods and structures for packaging semiconductor chips, a process critical for improving performance, reducing size, and managing heat in the high-performance processors that power modern mobile and consumer electronic devices.
• Key Procedural History: The complaint does not reference any prior litigation, inter partes review proceedings, or licensing history concerning the patents-in-suit.

Case Timeline

Date	Event
2012-09-26	Priority Date for '768, '763, and '306 Patents
2016-09-16	Launch of iPhone 7 (first listed generation of Accused Products)
2021-08-31	U.S. Patent No. 11,107,768 Issued
2022-12-27	U.S. Patent No. 11,538,763 Issued
2024-02-06	U.S. Patent No. 11,894,306 Issued
2025-07-07	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 11,107,768 - "Chip Package"

• Issued: August 31, 2021

The Invention Explained

• Problem Addressed: The patent's background describes challenges in microelectronic device miniaturization, where the metal interconnections between components can degrade circuit performance due to parasitic capacitance and resistance. It also notes that while using glass as a substrate interposer is cost-effective, forming reliable through-glass vias (TGVs) is difficult. U.S. Patent 11107768, col. 1:28-44 U.S. Patent 11,107,768, col. 2:1-10
• The Patented Solution: The patent proposes a specific chip package architecture built on a polymer or glass-like layer. This structure involves precisely defined metal plugs passing through the polymer layer to connect a semiconductor chip to an external interconnection scheme, which includes multiple metal layers and bumps for external connection. The detailed description outlines a manufacturing process using molds and layered deposition to create this high-density package. U.S. Patent 11,107,768, col. 5:11-7:8
• Technical Importance: The described packaging technology aims to achieve a higher density of input/output connections and improved electrical performance in a compact form factor, which is a key enabler for powerful processors in space-constrained mobile devices. U.S. Patent 11,107,768, col. 1:45-64

Key Claims at a Glance

• Asserted Claims: The complaint asserts claims 1-5, 7-8, 10-11, 14-15, 16-17, 19-20, 22-23, and 25-28 Compl. ¶27
• Independent Claim 1 requires:
  • A "first polymer layer" with a specific thickness (100-300 micrometers) and coefficient of expansion (3-10 ppm/°C).
  • A "first metal plug" and a "second metal plug" made of copper, vertically situated in through vias in the polymer layer, with their top surfaces in the same horizontal plane.
  • A "first interconnection scheme" over the polymer layer with multiple, specific metal interconnects and another polymer layer.
  • A "first metal bump" over the interconnection scheme, containing tin.
  • A "first semiconductor chip" under the interconnection scheme with its own specific interconnect structure, including a copper layer of a defined thickness (5-30 micrometers).

U.S. Patent No. 11,538,763 - "Chip Package"

• Issued: December 27, 2022

The Invention Explained

• Problem Addressed: As a continuation of the '768 patent family, the '763 patent addresses the same technical challenges of signal degradation and interconnection density in miniaturized electronic devices. (U.S. Patent 11,538,763, col. 1:24-44).
• The Patented Solution: The '763 patent also discloses a chip package structure designed to improve interconnection. This iteration of the invention is defined using slightly different language, focusing on a "solid layer" that comprises silicon and oxygen and has distinct regions. The solution still centers on a specific arrangement of copper plugs, interconnects, and bumps to connect a semiconductor chip. U.S. Patent 11,538,763, col. 9:1-col. 10:54
• Technical Importance: The invention provides an alternative structural definition for an advanced semiconductor package that aims to deliver similar benefits of high density and improved performance for mobile processors. U.S. Patent 11,538,763, col. 1:55-64

Key Claims at a Glance

• Asserted Claims: The complaint asserts claims 1-5, 7, 9-15, and 17 Compl. ¶45
• Independent Claim 1 requires:
  • A "solid layer" comprising a "compound of silicon and oxygen," with a specific thickness (100-300 micrometers) and defined first and second regions.
  • A "plurality of copper plugs" in through vias within the second region of the solid layer.
  • Specific dimensional relationships for the first region relative to the through vias and plug pitch.
  • A "first interconnection scheme" over the solid layer with multiple metal interconnects and a polymer layer.
  • A "first metal bump" over the scheme, comprising a metal layer and a tin-containing layer.
  • A "first semiconductor chip" under the scheme with its own specific interconnect structure, including a copper layer of a defined thickness (5-30 micrometers).

U.S. Patent No. 11,894,306 - "Chip Package"

• Issued: February 6, 2024

The Invention Explained

The '306 patent, also part of the same family, describes a chip package structure focused on integrating multiple components. The asserted independent claim details a package with a "solid layer" made of a silicon and oxygen compound, an interconnection scheme, and at least two semiconductor chips positioned relative to multiple metal bumps. U.S. Patent 11,894,306, claim 10

Asserted Claims & Accused Features

• Asserted Claims: The complaint asserts claims 10-17, with Claim 10 being the independent claim Compl. ¶61
• Accused Features: The complaint alleges that the structure of the Accused Chips, which contain stacked processor and memory components, infringes the multi-chip configuration claimed in the '306 patent Compl. ¶¶63-78

III. The Accused Instrumentality

Product Identification

The complaint names a wide array of Apple consumer electronics as the "Accused Apple Products," including iPhone models from the iPhone 7 onward, various iPad and Apple Watch models, and others Compl. ¶21 The infringement allegations, however, are directed at the "Accused Chips" within these products, such as the Apple A10-A17 series processors and S4-S9 series watch chips Compl. ¶22

Functionality and Market Context

The complaint alleges these Accused Chips utilize "InFO PoP" (Integrated Fan-Out Package-on-Package) technology Compl. ¶22 This is a type of wafer-level packaging that enables the stacking of different semiconductor dies (e.g., a logic processor and a DRAM memory package) without a traditional substrate. This substrate-less approach allows for a thinner overall package profile, higher interconnection density, and improved electrical and thermal performance, all of which are critical for high-performance mobile devices where space and power efficiency are paramount Compl. ¶23 The complaint includes a diagram from chip manufacturer TSMC to illustrate the basic structure of an InFO PoP package, showing a logic die and a DRAM package connected through redistribution layers (RDLs) and through-InFO-vias (TIVs) Compl. ¶23, p. 5

IV. Analysis of Infringement Allegations

'768 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a chip package comprising: a first polymer layer having a first surface and a second surface opposite to said first surface... wherein said first polymer layer has a thickness between 100 and 300 micrometers and has a coefficient of expansion between 3 and 10 ppm/° C.;	The Accused Chips allegedly have a polymer layer with parallel surfaces that meets the claimed thickness and coefficient of expansion ranges. The complaint's annotated diagram identifies this layer.	¶31	col. 7:38-45
a first metal plug vertically in a first through via in said first polymer layer, wherein said first metal plug comprises a first copper layer...	The Accused Chips are alleged to have a metal plug, comprising copper, positioned vertically in a through via within the polymer layer.	¶32; ¶33	col. 6:44-47
a second metal plug vertically in a second through via in said first polymer layer... wherein a top surface of said second metal plug and a top surface of said first metal plug are in the same horizontal plane;	The Accused Chips are alleged to have a second metal plug whose top surface is coplanar with the first metal plug's top surface.	¶34; ¶35	col. 8:43-46
a first interconnection scheme over said first surface, wherein said first interconnection scheme comprises a first metal interconnect... a second metal interconnect... a third metal interconnect... and a second polymer layer...	The Accused Chips allegedly possess an interconnection scheme with multiple metal interconnects and a polymer layer built over the first polymer layer's surface, as shown in an annotated diagram.	¶36	col. 8:1-12
a first metal bump over said first interconnection scheme... wherein said first metal bump comprises a tin-containing layer;	The Accused Chips allegedly include metal bumps over the interconnection scheme that contain tin.	¶38; ¶39	col. 8:13-16
a first semiconductor chip under said first interconnection scheme, wherein said first semiconductor chip comprises a fourth metal interconnect... wherein said fourth metal interconnect is connected to said third metal interconnect.	The Accused Chips allegedly have a semiconductor chip (e.g., the logic die) under the interconnection scheme with a specified metal interconnect structure that connects to the scheme above it.	¶40; ¶41	col. 8:17-30

'763 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a solid layer having a first surface and a second surface... wherein said solid layer comprises a compound of silicon and oxygen, wherein said solid layer has a thickness between 100 and 300 micrometers...	The complaint alleges the Accused Chips have a "polymer layer" that it asserts is a "solid layer" comprised of silicon and oxygen and meets the claimed thickness. An annotated diagram shows this layer.	¶49	col. 7:10-21
a plurality of copper plugs in a plurality of through vias in said second region of said solid layer respectively...	The Accused Chips allegedly contain multiple copper plugs within through vias in a specified region of the solid layer.	¶50; ¶51	col. 9:15-21
a first interconnection scheme over said first surface, wherein said first interconnection scheme comprises a first metal interconnect... a second metal interconnect... and a first polymer layer over said first and second metal interconnects...	The Accused Chips are alleged to have an interconnection scheme with multiple interconnects and a polymer layer over the solid layer.	¶53	col. 9:32-48
a first metal bump over said first interconnection scheme, wherein said first metal bump comprises a second metal layer and a tin-containing layer...	The Accused Chips allegedly contain a metal bump with a metal layer and a tin-containing layer over the interconnection scheme.	¶55	col. 9:49-53
a first semiconductor chip under said first interconnection scheme, wherein said first semiconductor chip comprises a third metal interconnect... wherein said third copper layer has a thickness between 5 and 30 micrometers.	The Accused Chips are alleged to have a semiconductor chip with an interconnect structure that meets the claimed material and thickness requirements.	¶56; ¶57	col. 9:54-65

Identified Points of Contention

• Scope Questions: A primary issue for the '763 patent will be whether the accused "polymer layer" Compl. ¶49 can be construed as a "solid layer... compris[ing] a compound of silicon and oxygen" as required by Claim 1. This suggests a potential mismatch between the claim's quasi-inorganic material requirement and the typically organic nature of polymers used in packaging. For the '768 patent, a question may arise as to whether the "first polymer layer" limitation reads on the structure of a substrate-less fan-out package like InFO PoP.
• Technical Questions: The claims in both patents recite very specific numerical ranges for thickness and material properties (e.g., '768 Claim 1's coefficient of expansion between 3 and 10 ppm/°C). The complaint asserts these are met based on "information and belief" Compl. p. 1 A key question for the court will be what evidence supports the allegation that the accused chips, manufactured at high volume, meet these precise quantitative limitations.

V. Key Claim Terms for Construction

For the '768 Patent

• The Term: "first polymer layer"
• Context and Importance: This term defines the foundational substrate of the claimed chip package. The infringement analysis hinges on whether the reconstituted molding compound layer in Apple's accused InFO PoP technology, which is formed around the chip rather than acting as a pre-existing substrate, qualifies as the claimed "first polymer layer."
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification suggests interchangeability, stating "the glass layer 16 may be replaced by a polymer layer." U.S. Patent 11,107,768, col. 7:38-39 This could support reading the term on any polymer layer that serves the described structural function.
  • Evidence for a Narrower Interpretation: The detailed description of the manufacturing process shows the layer being formed from a "high temperature liquid" that solidifies, a process more akin to glass handling. U.S. Patent 11,107,768, col. 6:50-57 A party could argue the "polymer layer" must be one formed in a manner analogous to the described glass process, potentially narrowing its scope.

For the '763 Patent

• The Term: "solid layer ... comprises a compound of silicon and oxygen"
• Context and Importance: This term is central because the complaint alleges a "polymer layer" meets this definition Compl. ¶49 Practitioners may focus on this term because typical packaging polymers are organic (carbon-based), whereas compounds of silicon and oxygen are characteristic of inorganic materials like glass or silicone. The viability of the infringement claim for the '763 patent depends heavily on construing this term to cover the material used in Apple's chips.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The term "comprises" suggests the compound of silicon and oxygen could be just one component of the layer (e.g., a silica filler in a polymer matrix). The specification's discussion of both glass (primarily silicon/oxygen) and polymer layers for the substrate could support an interpretation that this claim term was intended to cover both embodiments. U.S. Patent 11,538,763, col. 7:10-21 U.S. Patent 11,538,763, col. 7:41-42
  • Evidence for a Narrower Interpretation: The specification's primary example for a silicon and oxygen-based layer is glass (e.g., soda-lime glass, boro-silicate glass) U.S. Patent 11,538,763, col. 7:10-21 A party may argue that to "comprise a compound of silicon and oxygen," the layer's primary structural matrix must be based on Si-O bonds (like glass or silicone), not merely contain it as a filler in an organic polymer.

VI. Other Allegations

• Indirect Infringement: The complaint does not contain allegations of indirect infringement (inducement or contributory infringement). The three counts are for direct infringement pursuant to 35 U.S.C. § 271(a) Compl. ¶¶27; Compl. ¶45; Compl. ¶61
• Willful Infringement: The complaint does not plead willful infringement. It does not allege that Apple had knowledge of the patents-in-suit prior to the filing of the lawsuit. The prayer for relief requests damages under 35 U.S.C. § 284, which includes the potential for enhancement, but no specific factual basis for willfulness is articulated in the body of the complaint Compl. p. 21, prayer b

VII. Analyst's Conclusion: Key Questions for the Case

This case presents a focused dispute over advanced semiconductor packaging technology. The outcome may turn on a few central questions:

1. A core issue will be one of definitional scope and material science: can the term "solid layer ... comprises a compound of silicon and oxygen" ('763 Patent) be construed to cover the alleged "polymer layer" Compl. ¶49 in the accused chips? The resolution will depend on claim construction and evidence regarding the actual material composition of the accused fan-out packaging.
2. A second key issue will be one of evidentiary proof: can the plaintiff demonstrate, through reverse engineering and expert testimony, that the accused Apple chips meet the highly specific and narrow quantitative limitations recited in the claims, such as the thickness of "between 100 and 300 micrometers" and a coefficient of expansion "between 3 and 10 ppm/°C" ('768 Patent, Claim 1)?
3. A final question is one of structural equivalency: does the architecture of Apple's accused InFO PoP technology, a substrate-less fan-out package, fall within the scope of the claimed "chip package" structures, which are described in the patents with specific layered configurations that may or may not map directly onto the accused design?