Longitude Licensing Ltd v. Qualcomm Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Longitude Licensing Ltd. and Marlin Semiconductor Limited (Ireland)
  • Defendant: Qualcomm Inc. (Delaware)
  • Plaintiff's Counsel: Mintz Levin Cohn Ferris Glovsky and Popeo PC
• Case Name: Longitude Licensing Ltd. v. Qualcomm Inc.
• Case Identification: 1:25-cv-01629, W.D. Tex., 11/24/2025
• Venue Allegations: Venue is based on Defendant Qualcomm having regular and established places of business in the Western District of Texas, including specific office locations in Austin, and allegedly committing acts of infringement within the district.
• Core Dispute: Plaintiffs allege that Defendant's semiconductor devices, including its Snapdragon series of system-on-chip (SoC) products, infringe four U.S. patents related to fundamental semiconductor circuit designs.
• Technical Context: The patents address common design challenges in modern integrated circuits, including glitch protection in filler cells, jitter reduction in phase-locked loops, linear signal generation for neural network applications, and charge pump stability.
• Key Procedural History: The currently operative pleading is a First Amended Complaint. The original complaint in the case was filed on October 8, 2025, a date which Plaintiffs cite as establishing actual notice for the purpose of willful infringement allegations.

Case Timeline

Date	Event
2009-02-04	'666 Patent Priority Date
2010-04-27	'666 Patent Issue Date
2011-07-20	'890 Patent Priority Date
2011-08-15	'442 Patent Priority Date
2013-02-05	'442 Patent Issue Date
2013-06-11	'890 Patent Issue Date
2017-09-29	'475 Patent Priority Date
2018-10-16	'475 Patent Issue Date
~2020-03-01	Exemplary Accused Product Launch (Samsung Galaxy S20 series with Snapdragon 865)
2025-10-08	Original Complaint Filing Date
2025-11-24	First Amended Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,705,666: Filler Circuit Cell (Issued Apr. 27, 2010)

The Invention Explained

• Problem Addressed: In modern integrated circuit (IC) design, unused space is occupied by "filler cells." The transistors within these cells must be tied to a stable voltage. However, connecting a transistor's gate directly to a power supply rail (e.g., Vdd or Vss) makes it vulnerable to damage from voltage glitches, such as those caused by electrostatic discharge (ESD) '666 Patent, col. 1:35-45
• The Patented Solution: The patent proposes a filler circuit cell that incorporates a "voltage stabilizing unit" between the power supply and the gate of a filler cell transistor '666 Patent, abstract This unit acts as a buffer, isolating the sensitive gate from direct connection to the power rail and thereby preventing damage from sudden voltage spikes '666 Patent, col. 3:9-16 The stabilizing unit itself is composed of a pair of transistors arranged to provide a stable voltage level '666 Patent, col. 2:33-36
• Technical Importance: This design enhances the reliability and robustness of complex ICs by protecting non-functional but still-present circuit elements from electrical damage during manufacturing or operation.

Key Claims at a Glance

• The complaint asserts claims "including but not limited to claim 12" Compl. ¶42
• Independent claim 12 requires:
  • A filler circuit cell, comprising:
  • a decoupled capacitor comprising a first MOS transistor, with its source and drain connected to a first voltage source; and
  • a voltage stabilizing unit disposed between the first voltage source, the gate of the first MOS transistor, and a second voltage source to prevent glitch-induced damage;
  • wherein the voltage stabilizing unit comprises a second MOS transistor and a third MOS transistor.

U.S. Patent No. 8,461,890: Phase and/or Frequency Detector, Phase-Locked Loop and Operation Method for the Phase-Locked Loop (Issued Jun. 11, 2013)

The Invention Explained

• Problem Addressed: Phase-Locked Loops (PLLs), which are essential for generating stable clock signals, often suffer from a "dead zone." This occurs when the phase difference between a reference signal and a feedback signal is too small for the detector to register, preventing the charge pump from making necessary corrections and leading to timing errors, or "jitter," in the output signal '890 Patent, col. 7:4-40
• The Patented Solution: The invention introduces a phase/frequency detector with a special delay circuit that prolongs the reset pulse sent to the detector's flip-flops '890 Patent, abstract This ensures that even for minuscule phase differences, the charge pump receives a pulse of sufficient duration to operate correctly, thereby eliminating the dead zone '890 Patent, col. 7:51-58 The invention also includes a control circuit that can dynamically adjust this delay based on the PLL's operating frequency, which allows for optimizing power and performance '890 Patent, col. 9:1-8
• Technical Importance: By solving the dead zone problem, this invention improves the accuracy and stability of clock signals generated by PLLs, which is critical for the correct functioning of high-speed digital and communication systems.

Key Claims at a Glance

• The complaint asserts claims "including but not limited to claim 1" Compl. ¶57
• Independent claim 1 requires:
  • a phase and/or frequency detector comprising first and second flip-flops configured to receive a reference signal and a frequency-divided signal, respectively;
  • a logic gate configured to receive the outputs from the flip-flops;
  • a control circuit for generating a delay control signal based on the frequency of an oscillating signal; and
  • a delay circuit configured to alter a prolonged period according to the delay control signal to generate a reset signal for the flip-flops.

U.S. Patent No. 10,102,475: Control Circuit for Generating Linear Term Signals (Issued Oct. 16, 2018)

The Invention Explained

• Problem Addressed: Performing linear multiplication, a key operation in artificial neural network algorithms, with analog transistor circuits naturally produces undesired quadratic byproducts '475 Patent, col. 1:35-50
• The Patented Solution: The patent discloses a control circuit with a specific arrangement of switches, capacitors, and an inverter. This circuit generates output currents proportional to the linear product of a data signal and a weighting signal, which effectively cancels the unwanted non-linear terms '475 Patent, abstract '475 Patent, col. 3:53-4:2
• Technical Importance: This design enables accurate linear multiplication in analog circuits, which is critical for applications such as artificial neural networks.

Key Claims at a Glance

• The complaint asserts claims "including but not limited to claim 1" Compl. ¶75
• The accused feature is a "control circuit within the clock buffer and selector circuit" of the accused products Compl. ¶77

U.S. Patent No. 8,368,442: Charge Pump (Issued Feb. 5, 2013)

The Invention Explained

• Problem Addressed: Charge pumps, which are core components of PLLs, can suffer from instability when charging and discharging currents become mismatched or vary with the output voltage, degrading performance '442 Patent, col. 1:52-62
• The Patented Solution: The invention provides a charge pump that includes a voltage regulator. This regulator dynamically adjusts the gate voltages of the charge pump's transistors to compensate for output voltage fluctuations, ensuring the charging and discharging currents remain stable and balanced '442 Patent, abstract
• Technical Importance: This design improves the stability and performance of charge pumps, which are critical components in PLLs and other high-speed circuit designs.

Key Claims at a Glance

• The complaint asserts claims "including but not limited to claim 1" Compl. ¶89
• The accused feature is a "charge pump within the transmit path" of the accused products Compl. ¶91

III. The Accused Instrumentality

Product Identification

The complaint identifies "Qualcomm semiconductor devices, integrated circuits, and other products," with a primary focus on the Qualcomm SDR865 integrated circuit and broader product lines such as the Snapdragon 8 Series, 800 Series, X Elite Series, and X Plus Series Compl. ¶35 Compl. ¶41 The Samsung Galaxy S20 series is identified as an exemplary end-product that incorporates the accused SDR865 circuit Compl. ¶51

Functionality and Market Context

The accused products are highly integrated SoCs that serve as the central processors for a wide range of high-end consumer electronics, including smartphones and laptops Compl. ¶22 The infringement allegations target specific, fundamental sub-circuits within these SoCs, including a start-up circuit, a frequency phase detector, a clock buffer circuit, and a transmit path charge pump Compl. ¶44 Compl. ¶59 Compl. ¶77 Compl. ¶91 The complaint asserts that these devices provide vital functionality to downstream products Compl. ¶50

IV. Analysis of Infringement Allegations

'666 Patent Infringement Allegations

The complaint provides an annotated circuit diagram, identified as Figure 13.14.4 from a "CircuitVision Analysis" of the Qualcomm SDR865, to illustrate its infringement theory for claim 12 Compl. ¶44 The diagram shows what the complaint identifies as a "filler cell within the start-up circuit for its voltage regulator output stage" Compl. ¶44

Claim Element (from Independent Claim 12)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
A filler circuit cell, comprising: a decoupled capacitor comprising a first MOS transistor, wherein the source and drain of the first MOS transistor is connected to a first voltage source;	The accused SDR865 allegedly includes a P-type MOS transistor (identified in a red dotted box) that functions as a decoupled capacitor, with its source and drain connected to a first voltage source (VP).	¶45	col. 2:51-54
and a voltage stabilizing unit disposed between the first voltage source, a gate of the first MOS transistor and a second voltage source to prevent damage for the gate of the first MOS transistor caused by sudden glitches,	The accused circuit allegedly includes a voltage stabilizing unit (identified in a pink box) positioned between the first voltage source (VP), the gate of the aforementioned first MOS transistor, and a second voltage source (VSS).	¶46	col. 3:4-16
wherein the voltage stabilizing unit comprises a second MOS transistor and a third MOS transistor.	The accused voltage stabilizing unit is alleged to comprise a second MOS transistor (identified in an orange box) and a third MOS transistor (identified in a purple box).	¶47	col. 2:33-36

'890 Patent Infringement Allegations

The complaint uses annotated diagrams from a technical analysis of the SDR865, including Figure 3.1, to map accused structures to the elements of claim 1 Compl. ¶59 The complaint identifies the accused circuit as a "frequency phase detector" Compl. ¶59 A diagram shows the alleged first and second flip-flops, which receive reference and feedback clock signals, respectively Compl. ¶60 Compl. ¶61

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a phase and/or frequency detector, comprising a first flip-flop... configured for receiving a reference signal...	The SDR865 allegedly includes a first flip-flop (the lower DFF2 in a red box) whose clock input receives a reference signal (X_PLL_REFCK+).	¶60	col. 5:27-46
a second flip-flop... configured for receiving a frequency-divided signal...	The SDR865 allegedly includes a second flip-flop (the upper DFF2 in an orange box) whose clock input receives a frequency-divided feedback signal (PLL_FBCK).	¶61	col. 5:27-46
a logic gate configured for receiving signals outputted from the first data-output terminal and the second data-output terminal;	The "Test Multiplexer 1" circuit is alleged to be the claimed logic gate, receiving outputs from the two flip-flops.	¶63	col. 5:58-60
a control circuit configured for generating a delay control signal according to the oscillating frequency of the oscillating signal;	The SDR865 allegedly includes a control circuit that generates delay control signals (e.g., X_TPLL_PHDDCT[0] through [4]).	¶64	col. 9:1-8
and a delay circuit configured for altering a prolonged period according to the delay control signal to generate a reset signal...	The "Delay 3" circuits are alleged to be the claimed delay circuit, receiving the delay control signal to generate a reset signal for the flip-flops.	¶65	col. 9:9-19

• Identified Points of Contention:
  • Scope Questions: For the '666 patent, a central dispute may arise over the term "filler circuit cell". The complaint identifies the accused structure as part of a functional "start-up circuit" Compl. ¶44, which raises the question of whether an active, operational circuit can be considered a "filler circuit," a term the patent's background associates with filling otherwise "unused area" '666 Patent, col. 1:22-23 For the '890 patent, a question is whether the accused "Test Multiplexer 1" Compl. ¶63 performs the function of the claimed "logic gate" during normal operation, or if it serves a different purpose (e.g., for test and diagnostics) that falls outside the claim's scope.
  • Technical Questions: The infringement analyses for all four patents rely on reverse-engineered circuit diagrams. A key technical question will be whether the alleged structures in the complex SDR865 SoC operate in the specific manner required by the claims. For instance, regarding the '890 patent, it will be a matter of evidence whether the accused "Delay 3" circuits function to "alter a prolonged period" to solve a dead zone problem, as the patent teaches.

V. Key Claim Terms for Construction

'666 Patent: "filler circuit cell" (Claim 12)

• Context and Importance: This term appears in the preamble of claim 12 and is likely to be treated as a claim limitation. The infringement case for this patent may depend entirely on whether the accused "start-up circuit" Compl. ¶44 is properly classified as a "filler circuit cell." Practitioners may focus on this term because it appears to create a potential mismatch between the claimed invention and the alleged infringing functionality.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent does not appear to provide an explicit definition that would broaden the term to include active circuits. A plaintiff might argue that any standard cell used to occupy space in a library-based design flow could be considered a filler cell, regardless of any secondary function.
  • Evidence for a Narrower Interpretation: The patent's background section states that in IC design, "unused area of a circuit is filled with filler cells" '666 Patent, col. 1:22-23 This language, along with the patent's title, suggests that a "filler circuit cell" is one whose primary purpose is to fill empty space, which may support an interpretation that excludes essential, active circuits like a "start-up circuit."

'890 Patent: "delay circuit configured for altering a prolonged period" (Claim 1)

• Context and Importance: The novelty of the '890 patent centers on this dynamically adjustable delay to eliminate the PLL's dead zone. The infringement allegation hinges on showing that the accused "Delay 3" circuits Compl. ¶65 meet this functional limitation. The construction of "altering a prolonged period" will be critical to determining if a functional match exists.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim language itself is general, not specifying a particular mechanism for alteration. This may support a construction that covers any circuit that controllably changes a delay period used for a reset pulse. The specification notes the delay circuit "is configured for altering a prolonged period according to the delay control signal" '890 Patent, col. 2:19-21
  • Evidence for a Narrower Interpretation: The patent illustrates the delay circuit with a specific embodiment comprising a series of buffers and MOS transistors '890 Patent, FIG. 14 A defendant may argue that the term should be limited to structures similar to this disclosed embodiment, potentially excluding the accused "Delay 3" circuits if they operate on a different principle.

VI. Other Allegations

• Indirect Infringement: The complaint alleges both induced and contributory infringement for all asserted patents. The inducement allegations are based on Qualcomm allegedly designing its products to infringe and providing them to customers and partners with the knowledge and intent that they would infringe Compl. ¶33 Compl. ¶49 Compl. ¶68 Compl. ¶82 Compl. ¶97 The contributory infringement allegations assert that the accused products are a material part of the inventions, are especially adapted for infringement, and have no substantial non-infringing uses Compl. ¶34 Compl. ¶50 Compl. ¶69 Compl. ¶83 Compl. ¶98
• Willful Infringement: Plaintiffs allege willful infringement based on Defendant's continued infringement after having actual notice of the asserted patents, with notice established "at least as early as the filing of the Original Complaint" on October 8, 2025 Compl. ¶32 Compl. ¶39

VII. Analyst's Conclusion: Key Questions for the Case

This case presents a classic dispute over the application of semiconductor circuit patents to a complex, mass-market SoC. The outcome will likely depend on the court's resolution of several key technical and legal questions:

• A core issue will be one of definitional scope: Can the term "filler circuit cell" from the '666 patent, which the specification links to "unused area," be construed to cover an active, functional "start-up circuit" as alleged in the complaint?

• A second central issue will be one of operational function: Does the accused "Test Multiplexer 1" in the SDR865 perform the logical function of the "logic gate" claimed in the '890 patent during normal operation, or does it serve a non-infringing purpose, such as for diagnostics, that falls outside the claim?

• An overarching evidentiary question will be one of structural and functional mapping: Across all four asserted patents, which claim specific circuit architectures to solve common industry problems, the case will turn on whether the detailed circuit implementations within Qualcomm's accused Snapdragon products, as revealed through technical analysis, truly embody the structures and perform the functions precisely as required by the patent claims.