DCT

5:25-cv-10399

Synopsys Inc v. Real Intent Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 5:25-cv-10399, N.D. Cal., 02/19/2026
  • Venue Allegations: Venue is alleged to be proper as Defendant is a California corporation with its principal place of business in Sunnyvale, California, which resides in the Northern District of California.
  • Core Dispute: Plaintiff alleges that Defendant's electronic design automation (EDA) software products for static verification infringe nine U.S. patents related to verifying the functionality and integrity of integrated circuit (IC) designs.
  • Technical Context: The lawsuit concerns static verification tools used in the EDA industry, which are essential for identifying design flaws in complex ICs and Systems-on-a-Chip (SoCs) before the costly manufacturing process.
  • Key Procedural History: The complaint notes that the parties previously litigated claims on six of the same patents-in-suit in the Western District of Texas. That case was dismissed in December 2025 for improper venue after nearly a year of litigation, including venue-related discovery. The complaint also alleges Defendant had knowledge of several patents-in-suit due to their citation by USPTO examiners during the prosecution of Defendant's own patent applications or by Defendant itself in its patent applications.

Case Timeline

Date Event
2002-04-09 '733 Patent Priority Date
2006-01-31 '733 Patent Issue Date
2010-10-05 '560 Patent Priority Date
2010-09-20 '513 Patent Priority Date
2011-01-13 '706 Patent Priority Date
2012-03-09 '173 Patent Priority Date
2012-10-05 '993 Patent Priority Date
2013-10-31 '948 Patent Priority Date
2013-12-10 '173 Patent Issue Date
2014-02-11 '513 Patent Issue Date
2014-02-11 '560 Patent Issue Date
2014-07-22 '993 Patent Issue Date
2014-10-07 '706 Patent Issue Date
2015-08-21 '394 Patent Priority Date
2016-09-15 Defendant allegedly cites '513 patent in its own patent application
2016-06-30 '773 Patent Priority Date
2016-12-27 '948 Patent Issue Date
2017-10-17 '394 Patent Issue Date
2018-01-01 Defendant allegedly searched for and reviewed Plaintiff's patents (Approx. Date)
2019-05-14 '773 Patent Issue Date
2020-02-07 Defendant allegedly became aware of '394 patent via USPTO citation
2020-04-03 Defendant allegedly became aware of '773 patent via USPTO citation
2025-03-27 Prior lawsuit filed in W.D. Tex. on six of the patents-in-suit
2025-12-01 Prior W.D. Tex. case dismissed for improper venue (Approx. Date)
2026-02-19 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,607,173 - "Hierarchical Bottom-Up Clock Domain Crossing Verification"

  • Patent Identification: U.S. Patent No. 8,607,173, issued December 10, 2013.

The Invention Explained

  • Problem Addressed: The patent addresses the complexity and time-consuming nature of verifying clock-domain crossings (CDCs) in modern, large-scale IC designs (Compl. ¶28, citing '173 Patent, col. 1:17-21). Prior art methods that analyzed the entire IC at once or partitioned the design often resulted in long runtimes and incomplete verification (Compl. ¶29, citing '173 Patent, col. 1:22-56).
  • The Patented Solution: The invention provides a hierarchical, "bottom-up" method for CDC verification Compl. ¶¶29-30 The method involves independently verifying lower-level design blocks (modules), replacing each verified block with a corresponding simplified "abstraction module," and then iteratively moving up the design hierarchy to verify higher-level blocks that incorporate these abstractions '173 Patent, col. 1:63-2:9 '173 Patent, Fig. 6 This approach is intended to reduce the complexity and duration of verification cycles Compl. ¶33
  • Technical Importance: This hierarchical approach was presented as an unconventional method that enabled more efficient and complete verification of complex SoC designs, overcoming the limitations of prior art methods (Compl. ¶31, citing '173 Patent, col. 1:42-46).

Key Claims at a Glance

  • The complaint asserts independent claim 1 and dependent claims 2, 4, and 5 (Compl. ¶¶101; Compl. ¶111).
  • Independent Claim 1 requires a method comprising the following essential elements:
    • identifying a module from a plurality of modules that has not been previously abstracted or changed;
    • performing a CDC verification on the module in a bottom-up fashion;
    • replacing the verified module with a corresponding abstraction module that correctly identifies clock-domains for its inputs and outputs;
    • repeating the identifying, performing, and replacing steps for remaining modules; and
    • storing an updated model of the IC comprising at least one replaced module.

U.S. Patent No. 9,792,394 - "Accurate Glitch Detection"

  • Patent Identification: U.S. Patent No. 9,792,394, issued October 17, 2017.

The Invention Explained

  • Problem Addressed: The patent concerns the detection of "glitches"-transient, unwanted signal changes-that can cause malfunctions in ICs, especially for signals crossing different clock domains (Compl. ¶37, citing '394 Patent, col. 1:28-32). Conventional glitch detection tools were prone to producing a large number of false positives because they failed to properly account for "glitch-blocking circuitry" that might render a potential glitch harmless (Compl. ¶47, citing '394 Patent, col. 6:26-29).
  • The Patented Solution: The invention describes a computer-implemented method that analyzes a circuit design at two different levels of abstraction: a higher-level (e.g., Register-Transfer Level or RTL) and a lower-level (e.g., a netlist) (Compl. ¶42, citing '394 Patent, col. 1:67-2:4). The method first analyzes the higher-level abstraction to identify glitch-blocking circuits and their corresponding enable signals (Compl. ¶43, citing '394 Patent, col. 6:42-44). It then analyzes the lower-level abstraction to determine if a potential glitch is actually blocked when the enable signal is set to its blocking value. If the glitch is not blocked, it is identified as a design problem (Compl. ¶43, citing '394 Patent, col. 6:63-7:2; '394 Patent, Fig. 3).
  • Technical Importance: This dual-abstraction analysis was designed to more accurately determine if a glitch is truly problematic, thereby reducing false positives and allowing designers to focus on genuine design flaws Compl. ¶47

Key Claims at a Glance

  • The complaint asserts independent claim 1 and dependent claims 2, 3, 4, and 8 (Compl. ¶¶129; Compl. ¶142).
  • Independent Claim 1 requires a method for detecting design problems, comprising the following essential elements:
    • analyzing a higher-level abstraction to identify a set of glitch-blocking circuits and, for each, an enable signal and a corresponding blocking value;
    • analyzing a lower-level abstraction (generated from the higher-level one) to identify a possible glitch in a first signal;
    • identifying a first enable signal in the lower-level abstraction that corresponds to a glitch-blocking circuit; and
    • detecting a design problem if the possible glitch is not blocked when the first enable signal is assigned the first blocking value.

U.S. Patent No. 8,650,513 - "Reducing X-Pessimism in Gate-Level Simulation and Verification"

  • Patent Identification: U.S. Patent No. 8,650,513, issued February 11, 2014.
  • Technology Synopsis: The patent addresses "X-pessimism," a phenomenon in circuit simulation where the propagation of indeterminate ("X") values leads to simulation results that are more pessimistic than the behavior of the actual silicon (Compl. ¶¶49-51, Compl. ¶citing '513 Patent, Compl. ¶¶col. 5:53-57). The patented solution involves identifying parts of a design with reconvergent paths that are likely to exhibit X-pessimism and adding a "correcting block" to the design to produce a more accurate, non-pessimistic output value during simulation (Compl. ¶52, citing '513 Patent, col. 7:66-8:3).
  • Asserted Claims: The complaint asserts independent claims 1, 21, and 25 (Compl. ¶¶160; Compl. ¶166; Compl. ¶173).
  • Accused Features: The accused products, including Ascent XV and Verix SimFix, are alleged to implement X-pessimism reduction by using static analysis to identify potential pessimism and adding correction logic (Compl. ¶163; Compl. ¶164; Compl. ¶165).

U.S. Patent No. 8,359,560 - "Methods and Systems for Debugging Equivalent Designs Described at Different Design Levels"

  • Patent Identification: U.S. Patent No. 8,359,560, issued February 11, 2014.
  • Technology Synopsis: The patent addresses the "technological bottleneck" of debugging and tracing signals between different design levels, such as the RTL and gate levels (Compl. ¶57, citing '560 Patent, col. 1:30-33). The invention enables synchronous debugging by using at least two debugging processes, each presented in a set of windows corresponding to a design level. When a user interacts with a signal in one set of windows (e.g., RTL), the corresponding signal in the other set of windows (e.g., gate level) is automatically selected, reducing debugging time (Compl. ¶58, citing '560 Patent, col. 1:37-39).
  • Asserted Claims: The complaint asserts independent claims 1 and 5 (Compl. ¶¶189; Compl. ¶200).
  • Accused Features: The accused products iDebug and SafeConnect are alleged to provide a debugging environment that obtains signal correlation information between RTL and Netlist levels and allows a user to select a signal in one level and have the corresponding signal selected in the other (Compl. ¶¶193-196).

U.S. Patent No. 10,289,773 - "Reset Domain Crossing Management Using Unified Power Format"

  • Patent Identification: U.S. Patent No. 10,289,773, issued May 14, 2019.
  • Technology Synopsis: The patent addresses inefficiencies in handling reset domain crossings (RDCs) and power domain crossings (PDCs), which were traditionally managed separately, leading to redundant isolation circuitry (Compl. ¶63, citing '773 Patent, col. 2:18-21). The invention proposes analyzing both HDL (for RDCs) and Unified Power Format (UPF, for PDCs) descriptions to identify signals that cross both domain types, allowing for the use of shared, non-redundant isolation gates to improve circuit size and performance (Compl. ¶66, citing '773 Patent, col. 3:6-9; '773 Patent, col. 3:17-30).
  • Asserted Claims: The complaint asserts independent claims 1 and 11, as well as several dependent claims (Compl. ¶¶216; Compl. ¶223).
  • Accused Features: The accused products Meridian RDC and SafeConnect are alleged to utilize both HDL and UPF descriptions to identify signals forming both RDCs and PDCs and generate reports on candidates for shared isolation structures (Compl. ¶¶218; Compl. ¶220-221).

U.S. Patent No. 9,529,948 - "Minimizing Crossover Paths for Functional Verification of a Circuit Description"

  • Patent Identification: U.S. Patent No. 9,529,948, issued December 27, 2016.
  • Technology Synopsis: The patent seeks to optimize functional verification by reducing the number of "crossover paths" (signal paths crossing power domains) that need to be evaluated Compl. ¶69 Instead of analyzing all paths, the method uses low-power information from UPF files to identify only the power state combinations relevant for functional verification, thereby generating a smaller, "functional" subset of crossover paths for analysis and reducing computational demand (Compl. ¶¶70-71, Compl. ¶citing '948 Patent, Compl. ¶¶col. 1:46-52; '948 Patent, Compl. ¶¶col. 2:53-59).
  • Asserted Claims: The complaint asserts independent claim 1 and several dependent claims (Compl. ¶¶244; Compl. ¶257).
  • Accused Features: The accused products (Meridian CDC, Meridian RDC, SafeConnect) are alleged to use a power design description (UPF) to generate a reduced set of "functional crossover paths" for analysis, excluding paths that are not active in allowed power states (Compl. ¶¶249; Compl. ¶253-255).

U.S. Patent No. 8,856,706 - "System and Method for Metastability Verification of Circuits of an Integrated Circuit"

  • Patent Identification: U.S. Patent No. 8,856,706, issued October 7, 2014.
  • Technology Synopsis: The patent addresses the problem of false violations in traditional CDC verification, which often relied on simple structural recognition of known synchronization circuits like FIFOs (Compl. ¶77, citing '706 Patent, col. 1:33-53). The invention provides a more comprehensive approach using "structural pruning" to systematically identify potential synchronization points for source-destination pairs and then determine if the source is properly synchronized, avoiding reliance on a-priori structural knowledge (Compl. ¶¶77; Compl. ¶81, citing '706 Patent, col. 2:46-48).
  • Asserted Claims: The complaint asserts independent claim 14 and several dependent claims (Compl. ¶¶277; Compl. ¶285).
  • Accused Features: The accused product Meridian CDC is alleged to perform metastability verification by determining source-to-destination paths, using structural pruning to identify synchronization points, and storing the synchronized or unsynchronized result (Compl. ¶¶280-284).

U.S. Patent No. 6,993,733 - "Apparatus and Method for Handling of Multi-Level Circuit Design Data"

  • Patent Identification: U.S. Patent No. 6,993,733, issued January 31, 2006.
  • Technology Synopsis: The patent presents a "look-ahead" design methodology to identify design errors earlier in the IC design process Compl. ¶85 Traditional design flows require costly repetitions when errors are found late (Compl. ¶85, citing '733 Patent, col. 1:61-63). The invention uses a "constraint engine" and "violations database" to collect constraint data and perform hierarchical and structural analysis, allowing violations detected at later stages to be "back-referenced" to the higher-level design for easier correction (Compl. ¶¶87-88, Compl. ¶citing '733 Patent, Compl. ¶¶col. 5:21-26).
  • Asserted Claims: The complaint asserts independent claim 35 and several dependent claims (Compl. ¶¶307; Compl. ¶313).
  • Accused Features: The accused products SafeConnect and iDebug are alleged to perform look-ahead design analysis by collecting constraint data in a database and performing hierarchical and structural analysis to detect and store violations (Compl. ¶¶309-312; Compl. ¶315).

U.S. Patent No. 8,788,993 - "Computer System for Generating an Integrated and Unified View of IP-Cores for Hierarchical Analysis of a System on Chip (SoC) Design"

  • Patent Identification: U.S. Patent No. 8,788,993, issued July 22, 2014.
  • Technology Synopsis: The patent addresses the difficulty of full-chip verification for large SoCs containing many third-party IP cores, where a "flat" analysis is not viable (Compl. ¶92, citing '993 Patent, col. 1:38-41). The invention creates verification-specific "abstracted views" for each IP core and then integrates these into a "unified abstracted view." This unified view allows different verification types (e.g., CDC, DFT, PM) to run on the same hierarchical design efficiently (Compl. ¶¶93-94, Compl. ¶citing '993 Patent, Compl. ¶¶col. 2:36-43; '993 Patent, Compl. ¶¶col. 4:14-18).
  • Asserted Claims: The complaint asserts independent claims 1, 4, and 5 (Compl. ¶¶330; Compl. ¶346).
  • Accused Features: The accused products Meridian CDC and Meridian RDC are alleged to create and use a "Meta-Database" that stores abstracted views of IP cores, which are then used to form a "unified abstracted view" for performing verification on the larger SoC design (Compl. ¶¶336-337).

III. The Accused Instrumentality

  • Product Identification: The complaint names a suite of Electronic Design Automation (EDA) software products from Defendant Real Intent, including: Meridian CDC, Meridian RDC, Meridian RXV, SafeConnect, Ascent XV, Verix SimFix, SimPortal, Ascent AutoFormal, Sentry, and iDebug (including iVision) Compl. ¶102 Compl. ¶130 Compl. ¶161 Compl. ¶190 Compl. ¶217 Compl. ¶245 Compl. ¶278 Compl. ¶308 Compl. ¶331
  • Functionality and Market Context: The accused products are static and formal verification tools used by IC designers to accelerate "early functional verification and advanced sign-off of digital designs" Compl. ¶7 Their alleged functionality includes hierarchical clock-domain crossing (CDC) and reset-domain crossing (RDC) verification, glitch detection and sign-off, X-pessimism reduction, and multi-level debugging Compl. ¶103 Compl. ¶132 Compl. ¶163 Compl. ¶192 The complaint presents visual evidence, such as a slide from a public presentation, illustrating the "hierarchical flow" allegedly implemented in the Meridian CDC product Compl. ¶105 Another slide depicts the alleged "Glitch Sign-off Flow" for the Meridian CDC and SafeConnect products Compl. ¶131 The complaint positions these products as direct competitors to Plaintiff Synopsys's own static verification tools Compl. ¶8 Compl. ¶122

IV. Analysis of Infringement Allegations

'173 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A method for clock-domain crossing (CDC) verification of a model of an integrated circuit (IC) comprising a plurality of modules... The Meridian CDC product is described as enabling "quick clock domain crossing verification, from individual blocks to billion-gate SoC designs." ¶103 col. 1:7-11
identifying a module from among the plurality of modules that has not been previously abstracted or that has not changed since a previous abstraction... The accused product allegedly operates with a "hierarchical flow" that identifies and verifies individual IP or block-level modules. ¶104 col. 1:63-67
performing a CDC verification on the module in a bottom-up fashion by a computer processor device; The accused product allegedly performs bottom-up CDC analysis, as shown in a workflow diagram from Defendant's online help materials depicting "BLOCK" and "TOP" level analysis. ¶105; ¶106 col. 2:1-2
replacing the module with a corresponding abstraction module that correctly identifies a corresponding clock-domain for each of the input and the output... Defendant's product allegedly uses a "meta-database" to store abstraction information for a given IC component, which is then used at higher levels of the design. A slide depicts this "CDC Meta-database" containing information such as port connectivity, clock trees, and synchronizers. ¶106; ¶107 col. 2:3-6
repeating the identifying, performing, and replacing for each of the remaining modules... The accused product's verification process is described as iterative; after an IP or block is verified, its CDC information is saved and "used at the top level for CDC verification" as higher-level subsystems are assembled. ¶108 col. 2:7-9
storing an updated model of the IC comprising at least a replaced module in storage. The accused product allegedly creates and stores an updated IC model that comprises the abstraction models (the "meta-database") created during the block-level verification process. ¶109; ¶110 col. 2:10-12
  • Identified Points of Contention:
    • Scope & Technical Questions: A central question will be whether the Defendant's "hierarchical flow" and "meta-database," as described in marketing materials, function in the specific, iterative manner required by claim 1. The court may need to determine if saving information to a "meta-database" is equivalent to the claim step of "replacing the module with a corresponding abstraction module," and whether assembling higher-level systems using this data constitutes "repeating the identifying, performing, and replacing" steps.

'394 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
...a method for detecting design problems in a circuit design... The accused products are used in a "Glitch Sign-Off Flow," which is described as a method for detecting design problems. ¶132 col. 1:67-2:1
analyzing a higher-level abstraction of the circuit design to identify (1) a set of glitch-blocking circuits, and (2) for each glitch-blocking circuit... (i) an enable signal... and (ii) a blocking value... The accused products allegedly analyze higher-level abstractions (RTL or "Block" level) to identify glitch-blocking circuits and their associated enable signals and blocking values. A marketing slide shows the accused products "detect[] synchronized CNTL signal(s) blocking or controlling DATA signals." ¶134; ¶136; ¶137 col. 6:42-44
analyzing a lower-level abstraction of the circuit design to identify a possible glitch in a first signal... The accused products are alleged to perform glitch detection at the "Gate-Level Netlist" or "NETLIST" level, which is generated from the higher-level (RTL) design. A slide shows analysis of both "RTL" and "NETLIST" levels. ¶134; ¶139 col. 6:44-50
identifying a first enable signal in the lower-level abstraction of the circuit design that corresponds to a glitch-blocking circuit that is supposed to block glitches in the first signal; The accused products allegedly identify corresponding circuitry and signals between the higher-level (RTL) and lower-level (NETLIST) abstractions to perform glitch detection. ¶140 col. 6:55-64
detecting a design problem in the circuit design in response to determining that the possible glitch in the first signal is not blocked... The accused products allegedly enable "glitch propagation" sign-off, which includes detecting design problems where glitches are not blocked. ¶141 col. 6:65-7:2
  • Identified Points of Contention:
    • Technical Questions: The infringement analysis may turn on what evidence the complaint provides that the accused products perform the specific sequence of claim 1: first analyzing the high-level abstraction to identify the "glitch-blocking circuit", and only then analyzing the low-level abstraction to see if a glitch is actually blocked. The functionality described in marketing materials must be shown to map to this specific claimed process.
    • Scope Questions: The definition of "glitch-blocking circuit" will be critical. The court will have to decide if this term is limited to the CDC synchronization circuits emphasized in the patent's examples or if it can be read more broadly to cover other logic structures that Defendant's products might identify.

V. Key Claim Terms for Construction

For the '173 Patent

  • The Term: "abstraction module"
  • Context and Importance: This term is the core of the invention; the method revolves around replacing verified modules with these abstractions. Whether Defendant's "meta-database" Compl. ¶106 constitutes an "abstraction module" will be a central point of dispute. Practitioners may focus on this term because its construction will likely determine whether the accused product's core data structure falls within the claim scope.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes it as "an abstracted model of the block that annotates its relevant CDC information" '173 Patent, col. 3:10-12 This general language may support a broader definition that could encompass various data structures, including the accused "meta-database."
    • Evidence for a Narrower Interpretation: Dependent claim 2, which is asserted, requires the "abstraction module" to include "an assumption for the input of the module and a constraint for an output port of the output of the module" '173 Patent, cl. 2 Dependent claim 4 further specifies that the "constraint comprises at least one of: module name, port name, clock domain, name of at least one of synchronizers, flip-flops (FFs), and latches" '173 Patent, cl. 4 A defendant may argue these dependent claims narrow the meaning of the term in the independent claim.

For the '394 Patent

  • The Term: "glitch-blocking circuit"
  • Context and Importance: The method's first step is to identify these circuits. The scope of this term will define what the accused tool must be capable of identifying at the higher-level abstraction. If the term is construed narrowly, it may be more difficult to prove infringement. Practitioners may focus on this term because the patent's examples seem to use it in a specific context (CDC), while the infringement allegation may rely on a broader application.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification states, "Synchronization circuitry can also act as glitch-blocking circuitry" ('394 Patent, col. 4:7-8, emphasis added). The use of "can also act as" suggests that other types of circuits could also be considered "glitch-blocking circuits," supporting a broader definition beyond just synchronizers.
    • Evidence for a Narrower Interpretation: The patent's background and detailed examples heavily focus on the context of CDC paths and synchronization circuits (e.g., '394 Patent, col. 1:28-32; '394 Patent, Fig. 1B). A defendant may argue that the term should be limited to the context provided by these specific embodiments, namely, circuits designed to handle clock-domain crossings.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges that Real Intent induces infringement by its customers across all asserted patents. The allegations state that Real Intent requires customers to enter into contracts to use the accused products, provides application engineers who instruct customers on how to use the infringing functionality, and advertises the benefits of the patented methods to encourage their use Compl. ¶¶116-121 Compl. ¶¶147-152
  • Willful Infringement: Willfulness is alleged for all asserted patents. The complaint alleges pre-suit knowledge based on multiple grounds: (1) a prior lawsuit filed by Synopsys against Real Intent in March 2025 involving six of the patents-in-suit Compl. ¶23; (2) Real Intent's alleged knowledge of the '513 patent since at least September 2016 from citing it in its own patent application Compl. ¶22; (3) examiner citations of the '394 and '773 patents during the prosecution of Real Intent's own patent applications Compl. ¶22; and (4) an alleged search and review of Synopsys's patent portfolio "around 2018" Compl. ¶24 The complaint further alleges that any lack of knowledge amounts to willful blindness Compl. ¶122

VII. Analyst's Conclusion: Key Questions for the Case

  • A core issue will be one of technical and definitional equivalence: does the functionality of the accused EDA tools, as evidenced by their actual operation versus their marketing materials, map onto the specific, multi-step processes required by the asserted claims? For example, the court will need to resolve whether Real Intent's use of a "meta-database" in its hierarchical flow is legally equivalent to the '173 patent's claimed method of serially "identifying", "performing" verification on, and "replacing" modules with an "abstraction module".
  • A second central question will concern willful infringement: can Synopsys prove by clear and convincing evidence that Real Intent acted with deliberate or reckless disregard for Synopsys's patent rights? The case will likely focus on whether the alleged instances of pre-suit knowledge-including citations in Real Intent's own patent prosecution and a prior, dismissed lawsuit-are sufficient to establish the requisite state of mind for enhanced damages.
  • A key evidentiary question will be one of functional implementation: does the analysis performed by the accused tools, particularly for glitch detection under the '394 patent, follow the specific two-level analytical sequence claimed-first identifying "glitch-blocking circuits" at a high level and then verifying their efficacy at a low level-or does it employ a different, non-infringing methodology to achieve a similar result?
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