DCT

3:26-cv-11609

SK hynix Inc v. Longhorn IP LLC

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 3:26-cv-11609, N.D. Cal., 10/08/2026
  • Venue Allegations: Plaintiff alleges venue is proper in the Northern District of California because a substantial part of the events occurred in the District, Defendants are subject to personal jurisdiction there, and Defendants directed infringement allegations and licensing demands at Plaintiff’s U.S. subsidiary, which resides and operates in the District.
  • Core Dispute: Plaintiffs seek a declaratory judgment that their High-Bandwidth Memory (HBM) and Dynamic Random-Access Memory (DRAM) products do not infringe eight U.S. patents owned by Defendants and/or that the patents are invalid.
  • Technical Context: The technology relates to advanced semiconductor fabrication, focusing on 3D packaging and interconnect structures like Through-Silicon Vias (TSVs), which are essential for high-performance memory and computing applications.
  • Key Procedural History: The complaint describes a complex history between the parties. Plaintiffs previously took a license from Trenchant Blade Technologies LLC, an affiliate of Defendant Longhorn IP, to a separate portfolio of patents. Plaintiffs allege that after a subsequent settlement between Longhorn IP and Taiwan Semiconductor Manufacturing Company (TSMC), the patents-in-suit were assigned to a newly-formed Longhorn IP affiliate, Mago Barca IP LLC (MBIP), to circumvent the existing license and assert new claims against Plaintiffs.

Case Timeline

Date Event
2008-06-27 U.S. Patent No. 8,334,170 Priority Date
2009-02-24 U.S. Patent No. 7,932,608 and 8,390,125 Priority Date
2010-05-26 U.S. Patent No. 9,570,324 Priority Date
2011-04-26 U.S. Patent No. 7,932,608 Issue Date
2012-11-15 U.S. Patent No. 9,177,914 and 9,530,690 Priority Date
2012-12-18 U.S. Patent No. 8,334,170 Issue Date
2013-03-05 U.S. Patent No. 8,390,125 Issue Date
2015-11-03 U.S. Patent No. 9,177,914 Issue Date
2016-12-27 U.S. Patent No. 9,530,690 Issue Date
2016-12-27 U.S. Patent No. 9,984,971 Priority Date
2017-02-14 U.S. Patent No. 9,570,324 Issue Date
2018-05-29 U.S. Patent No. 9,984,971 Issue Date
2018-07-30 U.S. Patent No. 11,410,877 Priority Date
2019-12-06 Longhorn IP affiliate Katana files suit against TSMC Compl. ¶41
2020-03-13 Longhorn IP and TSMC enter Collaboration Agreement Compl. ¶42
2020-05-08 Longhorn IP sends letter to SK hynix re: Trenchant patents Compl. ¶45
2022-07-05 SK hynix files DJ action against Longhorn IP and Trenchant Compl. ¶46
2022-08-09 U.S. Patent No. 11,410,877 Issue Date
2022-10-18 SK hynix and Trenchant enter into a patent license agreement Compl. ¶47
2023-08-21 TSMC files suit against Longhorn IP for breach of agreement Compl. ¶48
2024-11-19 TSMC and Longhorn IP settle and renew Collaboration Agreement Compl. ¶49
2025-01-10 Defendant MBIP is formed by Longhorn IP principal Compl. ¶51
2025-03-28 TSMC assigns Patents-in-Suit to MBIP Compl. ¶51
2025-06-11 Defendants send first assertion letter to SK hynix re: Patents-in-Suit Compl. ¶52
2025-10-05 Longhorn IP announces MBIP retained Cherian LLP Compl. ¶54
2026-05-06 Defendants send assertion letter regarding '914 patent Compl. ¶56
2026-05-28 Defendants send assertion letter regarding '324 patent Compl. ¶57
2026-10-08 Complaint for Declaratory Judgment filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,932,608 - "Through-Silicon Via Formed With a Post Passivation Interconnect Structure"

The Invention Explained

  • Problem Addressed: The patent addresses the challenge of creating reliable electrical connections to Through-Silicon Vias (TSVs) after the main passivation layers of a semiconductor die have been formed. Conventional post-passivation interconnect (PPI) processes can result in weak adhesion and high contact resistance between the TSV and the external contact-bonding pad (CB pad) (’608 Patent, col. 1:56-62).
  • The Patented Solution: The invention proposes a specific interconnect structure that sits on top of the CB pad to bridge the connection to the TSV. This structure is described as having two distinct parts: an "upper portion" formed on the pad that extends to connect to the TSV, and a "lower portion" that is adjacent to the pad and provides support '608 Patent, abstract ’608 Patent, col. 6:53-68 This T-shaped structure, formed in a separate via opening, is designed to cap the pad, improve adhesion, and lower resistance '608 Patent, Fig. 7
  • Technical Importance: As 3D stacked-die packages became more common, ensuring robust, low-resistance vertical connections via TSVs became critical for device performance and reliability.

Key Claims at a Glance

  • The complaint asserts that Defendants have alleged infringement of at least independent claim 1 Compl. ¶61
  • Independent Claim 1 requires:
    • An integrated circuit structure, comprising:
    • a semiconductor substrate;
    • a through-silicon via (TSV) extending into the semiconductor substrate;
    • a pad formed over the semiconductor substrate and spaced apart from the TSV; and
    • an interconnect structure formed over the semiconductor substrate and electrically connecting the TSV and the pad;
    • wherein the interconnect structure comprises an upper portion which is formed on the pad and extends to electrically connect the TSV; and a lower portion outside the TSV and adjacent and directly in contact with the pad Compl. ¶62

U.S. Patent No. 8,390,125 - "Through-Silicon Via Formed With a Post Passivation Interconnect Structure"

The Invention Explained

  • Problem Addressed: As a continuation of the ’608 patent, this patent also addresses the need for reliable PPI structures for TSVs in 3D integrated circuits, aiming to solve problems of weak adhesion and high contact resistance (’125 Patent, col. 1:49-62).
  • The Patented Solution: The ’125 patent refines the interconnect structure by explicitly adding a "dielectric layer" that surrounds the pad. The interconnect structure is formed over this dielectric layer, with its "lower portion" extending downward into the dielectric layer to be "co-elevational with the pad" ’125 Patent, abstract ’125 Patent, col. 6:40-50 This adds a specific geometric and material context not present in the parent patent.
  • Technical Importance: This refinement provides a more detailed architectural solution for isolating and supporting the PPI structure, which is crucial for managing electrical and mechanical properties in densely packed semiconductor devices.

Key Claims at a Glance

  • The complaint asserts that Defendants have alleged infringement of at least independent claim 1 Compl. ¶70
  • Independent Claim 1 requires:
    • An integrated circuit structure, comprising:
    • a semiconductor substrate;
    • a TSV extending into the substrate;
    • a pad formed over the substrate and spaced apart from the TSV;
    • a dielectric layer formed over the substrate and surrounding the pad; and
    • an interconnect structure formed over the dielectric layer, electrically connecting the TSV and the pad;
    • wherein the interconnect structure comprises an upper portion formed directly on the pad and extending laterally to connect the TSV, and a lower portion outside the TSV extending downwardly into the dielectric layer to be in direct contact with it and "co-elevational with the pad" Compl. ¶71

Multi-Patent Capsule Analysis

  • U.S. Patent No. 9,177,914, 9,530,690, and 9,984,971

    • Patent Identification: '914 Patent ("Metal Pad Structure Over TSV to Reduce Shorting of Upper Metal Layer," issued Nov. 3, 2015); '690 Patent ("Metal Pad Structure Over TSV to Reduce Shorting of Upper Metal Layer," issued Dec. 27, 2016); '971 Patent ("Methods of Forming Metal Pad Structures Over TSVs to Reduce Shorting of Upper Metal Layers," issued May 29, 2018) Compl. ¶¶36-38
    • Technology Synopsis: These related patents address the problem of "dishing," a defect where the center of a large metal pad is excessively polished away during chemical-mechanical planarization (CMP). The solution is a "slotted metal pad" design, where the pad is composed of an array of smaller metal bars separated by dielectric bars. This structure reduces the dishing effect and prevents metal stringers from causing shorts in subsequent layers ’914 Patent, abstract ’690 Patent, abstract
    • Asserted Claims: At least claim 1 of the '914 patent, claim 1 of the '690 patent, and claim 1 of the '971 patent are asserted Compl. ¶79 Compl. ¶88 Compl. ¶97
    • Accused Features: The interconnect structures within SK hynix's HBM devices are accused of infringement Compl. ¶79 Compl. ¶88 Compl. ¶97

  • U.S. Patent No. 8,334,170

    • Patent Identification: "Method for Stacking Devices," issued December 18, 2012 Compl. ¶35
    • Technology Synopsis: The patent describes a method for fabricating a stacked semiconductor device by applying uncured coating materials between each layer of chips as they are stacked. After all chips are stacked, the entire assembly undergoes a single thermal process to cure all the coating materials simultaneously, which reduces the thermal stress experienced by lower layers compared to sequential curing methods (’170 Patent, abstract).
    • Asserted Claims: At least claim 1 Compl. ¶106
    • Accused Features: The manufacturing processes for SK hynix's HBM devices Compl. ¶106

  • U.S. Patent No. 11,410,877

    • Patent Identification: "Source/Drain Contact Spacers and Methods of Forming Same," issued August 9, 2022 Compl. ¶39
    • Technology Synopsis: The patent discloses a method for forming source/drain contacts in advanced transistors. It uses a "contact etch stop layer" (CESL) and a uniquely formed "source/drain contact spacer" to improve device performance by, among other things, reducing parasitic resistance between the contact and the channel region (’877 Patent, abstract; ’877 Patent, col. 2:56-65).
    • Asserted Claims: At least claim 1 Compl. ¶115
    • Accused Features: The fabrication technology used in SK hynix DRAM and HBM devices Compl. ¶115

  • U.S. Patent No. 9,570,324

    • Patent Identification: "Method of Manufacturing Package System," issued February 14, 2017 Compl. ¶40
    • Technology Synopsis: The patent describes a method for creating a 2.5D package architecture. The process involves using a temporary carrier, forming TSVs in a substrate, adding a molding compound around the substrate, and then building interconnect structures, ultimately allowing an integrated circuit to be mounted on top ’324 Patent, abstract
    • Asserted Claims: At least claim 1 Compl. ¶124
    • Accused Features: SK hynix HBM devices "for use in advanced 2.5D package architectures" Compl. ¶124

III. The Accused Instrumentality

  • Product Identification: Plaintiffs' SK hynix HBM (High-Bandwidth Memory) and DRAM (Dynamic Random-Access Memory) products Compl. ¶¶61 Compl. ¶70 Compl. ¶115 The complaint specifically identifies "SK hynix HBM3, HBM3E, HBM4, and HBM4E products" as accused of infringing certain patents Compl. ¶81 Compl. ¶90
  • Functionality and Market Context: The complaint identifies SK hynix as "one of the world's leading semiconductor companies and a global supplier of advanced memory technologies" Compl. ¶4 HBM is a high-performance memory standard that involves vertically stacking multiple DRAM dies. These dies are interconnected using TSVs, a technology central to the patents-in-suit. The accused products represent Plaintiffs' advanced memory offerings and are significant in the high-performance computing market Compl. ¶¶1 Compl. ¶4 The complaint alleges that Defendants' infringement assertions target the fabrication methods and resulting structures of these devices Compl. ¶52

No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

As this is a complaint for declaratory judgment of non-infringement, the following charts summarize Plaintiffs' stated reasons for why their products do not infringe.

'608 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Non-Infringing Functionality Complaint Citation Patent Citation
an interconnect structure formed over the semiconductor substrate and electrically connecting the TSV and the pad; Plaintiff alleges its HBM products "do not have a claimed interconnect structure separate from a pad." ¶63 col. 6:53-56
wherein the interconnect structure comprises an upper portion which is formed on the pad and extends to electrically connect the TSV; and a lower portion outside the TSV and adjacent and directly in contact with the pad. Plaintiff alleges its products do not employ the two-part interconnect structure as required by the claim. ¶63 col. 6:57-62

'125 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Non-Infringing Functionality Complaint Citation Patent Citation
an interconnect structure formed over the dielectric layer and electrically connecting the TSV and the pad; Plaintiff alleges its HBM products "do not have a claimed interconnect structure separate from a pad." ¶72 col. 6:40-42
wherein the interconnect structure comprises an upper portion which is formed directly on the pad and extends laterally into direct electrical connection with the TSV; and a lower portion outside the TSV, and extending downwardly from the upper portion into the dielectric layer to be in direct contact with the dielectric layer and to be co-elevational with the pad. Plaintiff alleges its products do not employ the claimed interconnect structure with its specific two-part geometry and relationship to the dielectric layer. ¶72 col. 6:43-50
  • Identified Points of Contention:
    • Structural Scope Questions: The primary dispute for the '608 and '125 patents appears to be whether the accused products' features meet the claim requirement for an "interconnect structure" that is distinct from the "pad." Plaintiff alleges its products lack such a separate structure Compl. ¶63 Compl. ¶72 This raises the question: Does the architecture in the accused HBM products utilize a single, unitary component that performs the function of both the claimed "pad" and "interconnect structure," thereby falling outside the literal scope of the claims?
    • Technical Questions: For the '125 patent, a further question is whether the accused products have a structure with a lower portion extending into a dielectric layer to be "co-elevational with the pad" Compl. ¶71 The analysis may depend on the precise geometry and vertical alignment of features in the accused devices. Similarly, for the '914, '690, and '971 patents, a key factual question is whether the accused HBM products employ a "slotted metal pad" with "dielectric bars," as Plaintiff alleges they do not Compl. ¶81 Compl. ¶90 Compl. ¶99

V. Key Claim Terms for Construction

  • The Term: "interconnect structure" (as distinguished from the "pad")

  • Context and Importance: This term is central to the dispute over the '608 and '125 patents. Plaintiff’s non-infringement argument rests on the assertion that its products "do not have a claimed interconnect structure separate from a pad" Compl. ¶63 Compl. ¶72 The court's construction of whether the "interconnect structure" must be a physically separate and distinct element from the "pad" will be critical to the infringement analysis.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: A party might argue that the terms refer to functional roles rather than strictly separate physical objects, and that different portions of a single conductive body could satisfy the "pad" and "interconnect structure" limitations.
    • Evidence for a Narrower Interpretation: The claim language of the '608 patent recites "a pad" and "an interconnect structure" as separate elements in the list of components. Furthermore, the claim describes the interconnect structure's "upper portion" as being formed "on the pad," which suggests a sequential or layered manufacturing process creating two distinct components. The figures in the '608 patent (e.g., Fig. 7, element 34 on element 18) appear to depict the interconnect as a discrete T-shaped element formed on top of a separate pad, which may support a narrower construction requiring two separate physical structures.

  • The Term: "co-elevational with the pad" ('125 patent, claim 1)

  • Context and Importance: This term defines the required vertical positioning of the interconnect structure's lower portion. Infringement may turn on whether the accused devices meet this specific geometric constraint. Practitioners may focus on this term because small differences in vertical alignment, potentially arising from different manufacturing processes, could be dispositive of infringement.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: A party could argue "co-elevational" means generally at the same height or within the same horizontal plane, allowing for some manufacturing tolerance.
    • Evidence for a Narrower Interpretation: The claim requires the lower portion to extend "downwardly ... into the dielectric layer to be ... co-elevational with the pad" Compl. ¶71 This language, combined with patent figures (if available from prosecution history), might be used to argue for a strict requirement that the bottom surface of the lower portion must be perfectly coplanar with a specific surface of the pad.

VI. Other Allegations

  • Indirect Infringement: The complaint states that Defendants have accused SK hynix of inducing infringement by "distributors, resellers and end-users" Compl. ¶52 As a declaratory judgment action, the complaint seeks a declaration of non-infringement for both direct and indirect infringement Compl. ¶63
  • Willful Infringement: The complaint does not include a count for willful infringement, as it is a declaratory judgment action filed by the accused infringer. However, the complaint details an extensive pre-suit notification history, including a series of assertion letters from Defendants and their counsel beginning in June 2025 Compl. ¶¶52-57 This documented history of pre-suit knowledge could be cited by Defendants in a potential counterclaim to support allegations of willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of structural definition: For the '608 and '125 patents, can the claims be read to cover an integrated conductive element, or must the "pad" and the "interconnect structure" be physically separate components as depicted in the '608 patent's figures? The resolution will depend on claim construction and a factual analysis of the accused HBM products' architecture.
  • A second key question will be one of factual correspondence: For the patents on slotted pads ('914, '690, '971) and contact etch stop layers ('877), the dispute will likely center on a direct technical comparison. Does the specific manufacturing process and resulting structure of SK hynix's HBM and DRAM devices actually include the claimed "slotted metal pad with dielectric bars" or a "contact etch stop layer" configured in the manner required by the claims?
  • Finally, a significant legal and commercial context overlays the technical dispute: Is MBIP’s patent assertion campaign a legitimate, independent enforcement action, or is it, as the complaint alleges, a deliberate attempt by the Longhorn IP enterprise to circumvent SK hynix’s prior patent license with Longhorn IP’s affiliate, Trenchant? The court may need to examine the corporate relationships and the intent behind the creation of MBIP and the transfer of the patents-in-suit.