Renesas Electronics America Inc v. Monterey Research LLC

I. Executive Summary and Procedural Information

Renesas Electronics America Inc. v. Monterey Research, LLC

• Parties & Counsel:
  • Plaintiff: Renesas Electronics America Inc. (California)
  • Defendant: Monterey Research, LLC (Delaware)
  • Plaintiff's Counsel: Morrison & Foerster LLP
• Case Identification: 3:24-cv-06223, N.D. Cal., 09/03/2024
• Venue Allegations: Plaintiff Renesas Electronics America Inc. alleges venue is proper because Defendant Monterey Research, LLC's principal place of business is in the Northern District of California.
• Core Dispute: Plaintiff seeks a declaratory judgment that its microcontroller and system-on-chip products do not infringe four of Defendant's patents related to semiconductor memory and circuit architecture.
• Technical Context: The technology at issue involves the fundamental design and operation of non-volatile memory cells and system-level-reset functions within microcontrollers, which are core components in a vast range of electronic devices.
• Key Procedural History: This declaratory judgment action follows a history of enforcement activities by Defendant Monterey. The complaint states Monterey sent letters accusing Plaintiff of infringement in August 2018 and March 2022. Additionally, Monterey filed a patent infringement lawsuit against Plaintiff's parent corporation and customers in the Eastern District of Texas on April 10, 2024, asserting the same four patents.

Case Timeline

Date	Event
2000-02-16	Priority Date for '300 Patent
2000-10-26	Priority Date for '688 Patent
2001-06-05	'300 Patent Issued
2003-09-16	Priority Date for '133 Patent
2006-08-08	'133 Patent Issued
2007-05-29	Priority Date for '968 Patent
2010-03-16	'968 Patent Issued
2010-11-02	'688 Patent Issued
2018-08-07	Monterey sends first letter to Renesas alleging infringement
2022-03-01	Monterey sends second letter to Renesas alleging infringement
2024-04-10	Monterey files suit against Renesas's parent in E.D. Texas
2024-09-03	Complaint for Declaratory Judgment filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,243,300 - "Substrate Hole Injection for Neutralizing Spillover Charge Generated During Programming of a Non-Volatile Memory Cell"

• Patent Identification: U.S. Patent No. 6,243,300, "Substrate Hole Injection for Neutralizing Spillover Charge Generated During Programming of a Non-Volatile Memory Cell," issued June 5, 2001 Compl. ¶10

The Invention Explained

• Problem Addressed: The patent's background section describes how, during the programming of a non-volatile memory cell, unwanted "spillover electrons" can become trapped, degrading the cell's performance and making the erase process slow and inefficient Compl. ¶10 '300 Patent, col. 2:15-18
• The Patented Solution: The invention proposes a method for erasing a memory cell by generating "neutralizing holes" in the silicon substrate and moving them into the cell's channel. These holes are intended to combine with and neutralize the problematic spillover electrons, enabling a faster and more effective erase operation '300 Patent, abstract '300 Patent, col. 2:6-14 This process is schematically illustrated in Figures 6A and 6B of the patent '300 Patent, figs. 6A-6B
• Technical Importance: This technique was designed to improve the speed and reliability of erasing multi-bit flash memory cells, a key factor in advancing memory density and performance '300 Patent, col. 2:15-18

Key Claims at a Glance

• The complaint alleges non-infringement of the patent generally, with Count I focused on the distinction between "multi-bit" and "single-bit" cells Compl. ¶26 This suggests that independent method claims directed to multi-bit cells, such as Claim 15, are at issue.
• Independent Claim 15 includes the following essential elements:
  • A method of erasing a two bit EEPROM cell that has spillover electrons.
  • Generating neutralizing holes in the substrate by biasing a first region of the cell.
  • Moving the neutralizing holes to the channel by applying a negative voltage to the gate.
  • Substantially neutralizing the spillover electrons with the moved holes.
• The complaint seeks a declaration of non-infringement for all claims of the patent Compl. ¶25

U.S. Patent No. 7,679,968 - "Enhanced Erasing Operation for Non-Volatile Memory"

• Patent Identification: U.S. Patent No. 7,679,968, "Enhanced Erasing Operation for Non-Volatile Memory," issued March 16, 2010 Compl. ¶11

The Invention Explained

• Problem Addressed: The patent identifies a problem where, during an erase operation, capacitive coupling between the memory cell's well and its word line can cause the word line voltage to rise undesirably. This disruption can delay or interfere with the erasing process '968 Patent, col. 2:1-11
• The Patented Solution: The invention specifies a timed sequence of applying voltages. First, a negative voltage is applied to the word line. Only after this negative voltage reaches a specific target level ("a predetermined voltage") is a positive voltage then applied to the well '968 Patent, abstract This timing delay is designed to allow the word line voltage to stabilize before the well voltage is applied, mitigating the disruptive effects of capacitive coupling '968 Patent, col. 2:31-41
• Technical Importance: By controlling the timing of voltage application, the method aims to achieve a faster, more stable, and more effective erasing operation for non-volatile memory cells '968 Patent, col. 2:40-41

Key Claims at a Glance

• The complaint asserts non-infringement of Claim 1 of the '968 patent Compl. ¶32
• Independent Claim 1 includes the following essential elements:
  • A semiconductor device comprising a memory cell array, a negative voltage generating circuit, and a positive voltage generating circuit.
  • The negative voltage generating circuit is for applying a negative voltage to a word line.
  • The positive voltage generating circuit is for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage.
• The complaint seeks a declaration of non-infringement for all claims of the patent Compl. ¶31

Multi-Patent Capsule: U.S. Patent No. 7,089,133 - "Method and Circuit for Providing a System Level Reset Function for an Electronic Device"

• Patent Identification: U.S. Patent No. 7,089,133, "Method and Circuit for Providing a System Level Reset Function for an Electronic Device," issued August 8, 2006 Compl. ¶12
• Technology Synopsis: The patent addresses the problem of imprecise power-on reset circuits in electronic devices '133 Patent, col. 1:16-25 It discloses a multi-tiered reset system that uses an initial imprecise reset, followed by a second "tunable" reset that is adjusted using stored calibration data, to ensure the device has sufficient supply voltage before beginning full operation '133 Patent, abstract
• Asserted Claims: The complaint specifically references Claim 1 Compl. ¶38
• Accused Features: The complaint alleges that Renesas's RL78 microcontrollers and other products do not infringe because they do not perform the claimed "second reset function comprising using a tunable monitor of said supply voltage" Compl. ¶38 The accused products include the M16C family, RA 6 Series, RX, and RL series microcontrollers Compl. ¶20

Multi-Patent Capsule: U.S. Patent No. 7,825,688 - "Programmable Microcontroller Architecture (Mixed Analog/Digital)"

• Patent Identification: U.S. Patent No. 7,825,688, "Programmable Microcontroller Architecture (Mixed Analog/Digital)," issued November 2, 2010 Compl. ¶13
• Technology Synopsis: The patent addresses the challenge of integrating and facilitating communication between programmable analog and digital circuits on a single semiconductor chip '688 Patent, col. 1:21-25 It describes a Programmable System-on-a-Chip (PSoC) architecture featuring a programmable interconnect structure and a bus that allows for communication of input/output data between all analog and digital blocks '688 Patent, abstract
• Asserted Claims: The complaint specifically references Claim 1 Compl. ¶44
• Accused Features: The complaint alleges that Renesas's RH850 devices do not infringe because they lack the claimed "bus coupling analog input/output data and digital input/output data," stating the accused devices "do not have a bus for transmitting both analog and digital data" Compl. ¶44

III. The Accused Instrumentality

Product Identification

• The accused instrumentalities are a range of Renesas microcontroller, analog, power, and System-on-Chip (SoC) products Compl. ¶2 Specific product families identified include the H8SX, RX600, RH850, M16C, RA Series, and RL78 series, which incorporate various generations of embedded flash memory technology (e.g., 90nm, 40nm, 28nm processes) Compl. ¶17 Compl. ¶18 Compl. ¶20 Compl. ¶21

Functionality and Market Context

• These products are sophisticated integrated circuits used in a wide array of electronic systems. The complaint focuses on the specific technical operation of their internal memory cells and reset circuits. Renesas alleges that the architecture and operation of these components are fundamentally different from what is required by the claims of the patents-in-suit. For example, it contends its RH850 devices use "single-bit flash EEPROM cells" Compl. ¶26 and that its RX600 devices do not follow the specific voltage application timing for erase operations alleged to be claimed by the '968 Patent Compl. ¶32 No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

'300 Patent Infringement Allegations

Claim Element (from Independent Claim 15)	Alleged Non-Infringing Functionality	Complaint Citation	Patent Citation
a method of erasing a two bit EEPROM cell...	The accused RH850 devices and other products are single-bit flash EEPROM cells, not two-bit or multi-bit cells as described in the patent.	¶26	col. 16:17-18
said generating neutralizing holes in said substrate comprises biasing a first region of said cell;	The complaint does not provide sufficient detail for analysis of this element.		col. 16:19-21
said moving said neutralizing holes to said channel comprises applying a negative voltage across a gate of said cell; and	The complaint does not provide sufficient detail for analysis of this element.		col. 16:22-24
substantially neutralizing said spillover electrons with said neutralizing holes moved to said channel.	The complaint does not provide sufficient detail for analysis of this element.		col. 16:25-27

• Identified Points of Contention:
  • Scope Question: A central issue is whether the term "two bit EEPROM cell," as used in the patent, can be construed to read on the "single-bit flash EEPROM cells" that Renesas alleges are in its accused products Compl. ¶26
  • Technical Question: A factual dispute will likely arise over the actual structure and operation of the memory cells within Renesas's accused microcontrollers.

'968 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Non-Infringing Functionality	Complaint Citation	Patent Citation
a memory cell array having a plurality of non-volatile memory cells;	The accused RX600 devices contain non-volatile memory. This element does not appear to be in dispute.	¶30	col. 5:51-53
a negative voltage generating circuit for applying a negative voltage to a word line of the memory cell array during an erasing operation of the memory cell array; and	The complaint does not provide sufficient detail for analysis of this element.	¶32	col. 5:54-57
a positive voltage generating circuit for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage...	The accused RX600 devices do not apply a negative voltage to a word line before applying a positive voltage to the well. The operational sequence is different from that claimed.	¶32	col. 5:58-61

• Identified Points of Contention:
  • Technical Question: The primary dispute is factual and operational: What is the precise sequence and timing of voltage application during the erase cycle in the accused RX600 devices?
  • Evidentiary Question: The case may turn on what evidence (e.g., circuit diagrams, datasheets, testing) can be produced to demonstrate the actual operational characteristics of the accused products' erase function.

V. Key Claim Terms for Construction

For the '300 Patent

• The Term: "two bit EEPROM cell" / "multi-bit flash ... cells"
• Context and Importance: The entirety of Renesas's non-infringement argument in Count I rests on this term. Renesas contends its products use "single-bit" cells, creating a direct conflict with claims requiring a "multi-bit" or "two bit" structure Compl. ¶26 Practitioners may focus on this term as its construction could be dispositive for the '300 patent.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent's general summary refers to "a method of erasing a memory cell" without the "two bit" limitation, which may support an argument that the invention is not strictly limited to two-bit structures '300 Patent, col. 2:4-5
  • Evidence for a Narrower Interpretation: The specification heavily details and illustrates a "two bit flash EEPROM cell" embodiment, including figures and descriptions of its asymmetrical programming and reading '300 Patent, FIG. 2 '300 Patent, col. 4:34-38 '300 Patent, col. 5:46-54 This focus on a specific two-bit structure may support a narrower construction.

For the '968 Patent

• The Term: "when the negative voltage reaches a predetermined voltage"
• Context and Importance: This temporal clause in Claim 1 is the crux of the non-infringement argument in Count II Compl. ¶32 It defines the specific timing relationship between the negative word line voltage and the positive well voltage. Renesas alleges its products do not follow this sequence.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: A party might argue that "when" could encompass overlapping or simultaneous events, although this appears to be a difficult argument given the specification.
  • Evidence for a Narrower Interpretation: The specification explicitly states the benefit of delaying the application of the positive voltage: "By applying the positive voltage to the well... some time after the negative voltage is applied... the capacitive coupling... can be delayed" '968 Patent, col. 2:31-35 The flowchart in Figure 5 also clearly depicts a sequential process where the positive voltage application (S16) occurs only after the negative voltage has been checked and confirmed to be at its target level (S12), strongly supporting a narrow, sequential interpretation '968 Patent, fig. 5

VI. Other Allegations

• Indirect Infringement: The complaint, a declaratory judgment action, focuses on direct non-infringement and does not provide specific factual allegations for analysis of indirect infringement theories.
• Willful Infringement: While willfulness is not a claim made by the Plaintiff, the complaint establishes facts that could form the basis of a willfulness counterclaim by the Defendant. The complaint documents that Monterey provided notice of the patents-in-suit and its infringement allegations via letters sent on August 7, 2018, and March 1, 2022, long before the current action was filed Compl. ¶17 Compl. ¶18

VII. Analyst's Conclusion: Key Questions for the Case

This declaratory judgment action presents several distinct technical and legal disputes across the four asserted patents. The resolution of the case will likely depend on the court's findings on the following key questions:

1. A core issue will be one of definitional scope and claim construction: Can the term "two bit EEPROM cell" from the '300 patent, which is described in the context of storing two distinct bits of data, be construed to cover the "single-bit" memory cells that Renesas alleges are used in its RH850 microcontrollers?

2. A central question will be one of technical operation: Does the erase function in Renesas's RX600 devices operate with the specific, sequential voltage timing described in claim 1 of the '968 patent, or does it follow a different operational sequence, as Renesas contends?

3. An important architectural question will be one of functional equivalence: Does the bus architecture in Renesas's RH850 devices meet the '688 patent's requirement for a bus that couples both analog and digital input/output data, or is there a fundamental mismatch in the system's data-handling architecture?