Netlist Inc v. Micron Technology Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Netlist, Inc. (Delaware)
  • Defendant: Micron Technology, Inc. (Delaware); Micron Semiconductor Products, Inc. (Idaho)
  • Plaintiff's Counsel: Irell & Manella LLP
• Case Identification: 8:26-cv-02167, C.D. Cal., 08/10/2026
• Venue Allegations: Venue is alleged based on Defendants' commission of infringing acts within the district and their maintenance of a regular and established place of business in Irvine, California.
• Core Dispute: Plaintiff alleges that Defendant's DDR5 memory modules, including components such as RDIMMs and MRDIMMs, infringe patents related to on-module testing architectures and local clock signal generation.
• Technical Context: The dispute is in the high-performance memory module sector, focusing on DDR5 SDRAM technology, which is critical for servers, cloud computing, and artificial intelligence applications requiring high bandwidth and reliability.
• Key Procedural History: The complaint highlights Netlist's history of successful patent litigation, citing jury verdicts against Samsung and Micron in 2023 and 2024, which may be presented to establish the commercial success of its patented technologies and potentially support claims for willful infringement.

Case Timeline

Date	Event
2008-04-14	'523 Patent - Earliest Priority Date
2013-07-27	'407 Patent - Earliest Priority Date
2019-02-26	'523 Patent - Issue Date
2023-04-21	Jury verdict in Netlist v. Samsung
2024-05-23	Jury verdict in Netlist v. Micron
2024-11-22	Jury verdict in Netlist v. Samsung
2026-07-07	'407 Patent - Issue Date
2026-08-10	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 10,217,523 - "Multi-Mode Memory Module With Data Handlers," issued February 26, 2019 ('523 Patent)

The Invention Explained

• Problem Addressed: The patent's background describes the difficulty of testing memory modules and isolating faults during system-level operation, noting that conventional memory testing often requires external equipment or significant involvement from the system's main memory controller '523 Patent, col. 1:24-51
• The Patented Solution: The invention is a memory module with a dual-mode architecture facilitated by an on-board "control module" and "data module" '523 Patent, abstract In a "first mode" (normal operation), these components pass signals between the system memory controller and the memory devices '523 Patent, col. 6:13-28 In a "second mode" (test mode), the on-board logic is configured to "isolate the memory devices from being accessed by the system memory controller" and use its own logic to generate and verify test patterns, enabling on-module self-testing '523 Patent, col. 6:29-50 '523 Patent, Fig. 3
• Technical Importance: This approach allows for faster, more granular testing of memory modules at their target operational speed without requiring extensive external equipment or system-level resources '523 Patent, col. 3:52-58

Key Claims at a Glance

• The complaint asserts at least Claim 1 Compl. ¶35
• Independent Claim 1 requires:
  • A memory module with memory devices on a circuit board.
  • A "data module" mounted on the board, coupled between the memory devices' data ports and the system memory bus, and including "data handler logic elements."
  • A "control module" mounted on the board and coupled to the data module, memory devices, and system memory bus.
  • The module must be operable in a "first mode" and a "second mode."
  • In the "first mode," the control module passes address/control signals from the system, and the data module propagates data signals between the memory devices and the system.
  • In the "second mode," the control module outputs its own address/control signals, and the data module is configured to "isolate the memory devices from being accessed by the system memory controller" and transmit data patterns from its own logic elements to the memory devices.
• The complaint reserves the right to assert additional claims Compl. ¶35

U.S. Patent No. 12,675,407 - "Memory Module with Local Clock Signals," issued July 7, 2026 ('407 Patent)

The Invention Explained

• Problem Addressed: The patent background notes that as memory speeds increase, distributing a single, synchronous clock signal across an entire memory module becomes difficult, leading to timing variations (skew) that can compromise performance and reliability '407 Patent, col. 2:1-17
• The Patented Solution: The invention describes a memory module architecture with distributed data buffers '407 Patent, abstract Circuitry on the module receives a main system clock and generates a plurality of "local clocks." Each local clock is sent to a specific, corresponding group of memory devices and has a "programmable phase relationship" with the system clock, allowing for independent timing adjustments for different sections of the module '407 Patent, col. 9:10-25
• Technical Importance: This distributed clocking architecture allows for finer timing control across the memory module, compensating for signal skews and enabling higher operational speeds and densities than would be possible with a single, globally distributed clock '407 Patent, col. 2:23-27

Key Claims at a Glance

• The complaint asserts at least Claim 1 Compl. ¶64
• Independent Claim 1 requires:
  • A memory module with a PCB and memory devices organized in a "plurality of groups."
  • Circuitry mounted on the PCB that is configurable to:
  • Receive a system clock and control/address (C/A) signals from the memory controller.
  • Generate module C/A signals in response.
  • Generate a "plurality of local clocks" corresponding to the plurality of groups of memory devices.
  • The local clocks must have "respective phase relationships with the system clock," with these phase relationships being "programmable independently of each other."
  • Output a respective local clock to its corresponding group of memory devices and "not to any other group."
• The complaint reserves the right to assert additional claims Compl. ¶64

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are Defendants' DDR5 memory products, including DDR5 Registered Dual In-line Memory Modules (RDIMMs), DDR5 Multiplexed Rank Dual In-line Memory Modules (MRDIMMs), and components thereof such as Registering Clock Drivers (RCDs), Multiplexed Registering Clock Drivers (MRCDs), and Multiplexed Rank Data Buffers (MDBs) Compl. ¶28 The complaint lists numerous specific product part numbers Compl. ¶29

Functionality and Market Context

• The complaint alleges these DDR5 memory modules provide significant upgrades over prior generations to support high bandwidth requirements for AI and other data-intensive workloads Compl. ¶27
• The Accused DDR5 MRDIMM products are described as using an on-DIMM multiplexer (comprising an MRCD and MDBs) to manage data across memory ranks, which is alleged to enable higher bandwidth and bus efficiency Compl. ¶38
• The Accused DDR5 RDIMM products are alleged to use an RCD to buffer command, address, and clock signals between the host controller and the DRAMs Compl. ¶6 Compl. ¶33
• The complaint alleges these products incorporate components from third-party "Chipset Partners" such as Rambus, Montage, and Renesas Compl. ¶30 A diagram provided in the complaint from Montage illustrates an MRDIMM architecture where a central MRCD communicates with multiple MDBs, which in turn interface with DRAM chips Compl. ¶42

IV. Analysis of Infringement Allegations

'523 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
A memory module accessible in a computer system by a system memory controller via a system memory bus, comprising:	The Accused DDR5 Products (e.g., MRDIMMs) are memory modules accessible by a system memory controller via a system bus.	¶37	col. 16:55-58
[1.a] memory devices mounted on a circuit board...	The Accused DDR5 Products contain multiple DRAM chips (memory devices) mounted on a printed circuit board.	¶40	col. 5:20-23
[1.b] a data module mounted on the circuit board and coupled between the data ports of the memory devices and the system memory bus, the data module including data handler logic elements;	The Accused DDR5 Products contain Multiplexed Rank Data Buffers (MDBs) that are mounted on the circuit board between the DRAM chips and the system bus and contain logic to manage data traffic.	¶42	col. 6:1-5
[1.c] a control module mounted on the circuit board and coupled to the [a] data module, [b] the address and control ports of the memory devices, and [c] the system memory bus;	The Accused DDR5 Products contain a Multiplexed Registering Clock Driver (MRCD) that is coupled to the MDBs (data module), the DRAMs, and the system memory bus to buffer and re-drive signals.	¶43	col. 6:6-12
[1.d] wherein the memory module is operable in any of a plurality of modes including a first mode and a second mode;	The Accused DDR5 Products are alleged to be operable in a normal read/write mode ("first mode") and in various training modes ("second mode"), such as "CA, CS, DFE and BCOM training modes."	¶44	col. 2:54-56
[1.e] wherein the control module in the first mode is configured to receive system address and control signals... and the data module in the first mode is configured to propagate one or more first data signals...	In normal operation, the MRCD (control module) receives and re-drives signals from the memory controller, and the MDBs (data module) buffer and re-drive data signals between the DRAMs and the controller.	¶¶45-47	col. 6:13-28
[1.f] wherein the control module in the second mode is configured to output second memory address and control signals... and the data module in the second mode is configured to isolate the memory devices... and to transmit one or more second data signals including data patterns provided by the data handler logic elements...	In a training mode (e.g., MWD training), the MRCD outputs control signals to the DRAMs, while the MDB generates internal test patterns to write to the DRAMs, allegedly isolating them from data from the host controller. A table in the complaint summarizes these training features.	¶¶48-53	col. 6:29-50

• Identified Points of Contention:
  • Scope Question: A central question will be whether the accused products' JEDEC-standard "training modes" (Compl. ¶44) qualify as the "second mode" (or "test mode") recited in the patent. The analysis will focus on whether the functions performed during training-such as the MDB generating its own data patterns-meet the claim requirement that the data module is "configured to isolate the memory devices from being accessed by the system memory controller" Compl. ¶51
  • Technical Question: The complaint alleges the MRCD functions as the "control module" and the MDBs function as the "data module" Compl. ¶¶42-43 The case may turn on whether this mapping is technically and legally sound, or if the functions of the claimed modules are fundamentally different from the operation of the accused MRCD/MDB chipset.

'407 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
A memory module operable in a computer system having a memory controller and a system bus...	The Accused DDR5 Products are memory modules operable in a computer system with a memory controller and system bus.	¶¶66-68	col. 18:10-15
[1.a] a printed circuit board (PCB) having connectors...	The Accused DDR5 Products comprise a PCB with edge connectors for electrical connections to the system bus.	¶¶70-72	col. 3:20-26
[1.b] memory devices mounted on the PCB and organized in a plurality of groups...	The DRAM chips on the Accused DDR5 Products are alleged to be organized into multiple groups (e.g., by rank and channel).	¶¶73-75	col. 6:25-30
[1.c] circuitry mounted on the PCB and configurable to: [1.c.1] receive from the memory controller a system clock... and input control and address (C/A) signals...	The RCD/MRCD circuitry on the accused products is alleged to receive a system clock and C/A signals from the memory controller. A diagram from Rambus is provided to show the RCD receiving these inputs.	¶¶76-77; ¶82	col. 3:60-64
[1.c.3] generate a plurality of local clocks corresponding, respectively, to the plurality of groups of the memory devices, the plurality of local clocks having respective phase relationships with the system clock, the respective phase relationships being programmable independently of each other;	The RCD/MRCD is alleged to generate multiple local clock signals (e.g., CK_AA, CK_AB) for different DRAM groups, with phase relationships that are programmable via JEDEC-specified control words.	¶¶81-85	col. 9:10-18
[1.c.5] output the plurality of local clocks to the memory devices, wherein a respective local clock... is output to a corresponding group of the memory devices and not to any other group...	Datasheets and diagrams allegedly show that each generated local clock signal is sent to only one respective group of DRAMs.	¶86	col. 9:10-18
...wherein the corresponding group of the memory devices is configurable to perform memory read or write operations by communicating data signals... in accordance with the respective local clock.	Because each DRAM group receives its own respective local clock, it is alleged to perform read/write operations in accordance with that clock.	¶91	col. 18:41-47

• Identified Points of Contention:
  • Scope Question: A key issue will be the construction of the phrase "programmable independently of each other" Compl. ¶81 The court will need to determine if the accused products' use of JEDEC-standard control words to set delay/phase values for different clock groups meets this "independently" requirement, or if the standard imposes interdependencies that fall outside the claim scope.
  • Technical Question: The complaint maps various signals from RCD/MRCD datasheets (e.g., CK_AA, CK_AB) to the claimed "plurality of local clocks" Compl. ¶81 The infringement analysis will likely examine whether these signals function as distinct, locally generated clocks for discrete groups of memory devices as claimed, or if they are merely buffered and fanned-out versions of a common clock signal.

V. Key Claim Terms for Construction

'523 Patent

• The Term: "data module... configured to isolate the memory devices"
• Context and Importance: This term is central to distinguishing the "second mode" from the "first mode." The infringement case for the '523 patent hinges on showing that the accused products' training modes perform this "isolation." The definition will determine whether generating test patterns internally, while the host may still be issuing commands, constitutes "isolation." Practitioners may focus on this term because the accused products operate according to industry standards, and the nature of this "isolation" will be a key technical and legal battleground.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification describes the data module in the test mode as generating data signals "instead of propagating data signals from the system memory controller" '523 Patent, col. 3:9-13 This language may support an interpretation where "isolation" means preventing the system controller's data from reaching the memory devices, even if control signals are still passed.
  • Evidence for a Narrower Interpretation: The claim language states the data module is configured to isolate the memory devices "from being accessed by the system memory controller" '523 Patent, col. 17:5-7 This could be argued to require a more complete functional or electrical separation, where the system memory controller cannot access the memory devices at all, a potentially higher bar than what is alleged to occur in the accused training modes.

'407 Patent

• The Term: "programmable independently of each other"
• Context and Importance: This term defines a critical feature of the claimed "plurality of local clocks." Micron's defense may argue that because its clock adjustments are made via a standardized set of control words Compl. ¶82, they are not truly "independent." The outcome of the case may depend on whether this claim language requires complete architectural independence in the programming mechanism or simply the ability to set the phase of one clock group without altering another.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim recites that the "respective phase relationships" are programmable independently. This could be interpreted to mean that the resulting phase of Clock A can be set to value X while the phase of Clock B is set to value Y, regardless of whether a common register or bus is used to program them.
  • Evidence for a Narrower Interpretation: The patent does not appear to provide an explicit definition of "independently." A defendant might argue that the ordinary meaning implies separate and distinct control mechanisms. The specification's focus on solving skew across the module by creating local timing domains could be used to argue for an interpretation requiring a degree of architectural separation beyond merely addressable registers.

VI. Other Allegations

• Indirect Infringement:

  • Plaintiff alleges induced infringement of both patents, stating that Micron provides specifications, datasheets, and instruction manuals that "encourage and facilitate" the infringing use of the Accused DDR5 Products Compl. ¶58 Compl. ¶93 Marketing materials noting "seamless integration into existing server infrastructures" are also cited as evidence of intent Compl. ¶59 Compl. ¶94
  • Plaintiff alleges contributory infringement, asserting the accused products have no substantial non-infringing use and constitute a material part of the patented inventions Compl. ¶61 Compl. ¶96

• Willful Infringement:

  • For the '523 Patent, willfulness is alleged based on Micron's purported knowledge of the patent "at least as of February and/or April 2015" and actual knowledge "no later than April 28, 2021" via a letter Compl. ¶62
  • For the '407 Patent, willfulness is alleged based on Micron's continued infringement after the complaint was filed and alleged awareness of the patent's underlying application (U.S. Application No. 18/935,410) even before the patent issued Compl. ¶97

VII. Analyst's Conclusion: Key Questions for the Case

This case presents a classic dispute over whether standardized commercial products fall within the scope of patent claims that describe functional architectures. The key questions for the court will likely be:

1. A question of functional equivalence for the '523 Patent: Do the JEDEC-standard "training modes" of the accused MRDIMMs, which involve an on-module component generating test patterns, perform the same function in substantially the same way to achieve the same result as the claimed "second mode" that "isolate[s] the memory devices from being accessed by the system memory controller"?

2. A question of definitional scope for the '407 Patent: Can the clocking architecture of the accused RCDs/MRCDs, which uses standardized control words to adjust timing for different clock output groups, satisfy the claim requirement that the phase relationships of the "plurality of local clocks" are "programmable independently of each other"?

3. An overarching question of intent and evidence: Given the allegations of long-standing knowledge of the patents and a history of litigation between the parties, a central issue will be whether Micron's conduct rises to the level of willful infringement, which will depend heavily on what evidence of knowledge, intent, and objective baselessness is presented during discovery and at trial.