BiTMICRO LLC v. Kingston Technology Co Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: BiTMICRO LLC (Delaware)
  • Defendant: Kingston Technology Company, Inc. (Delaware); Kingston Technology Corporation (California); Kingston Digital, Inc. (Delaware)
  • Plaintiff's Counsel: Prince Lobel Tye LLP
• Case Identification: 8:26-cv-01528, C.D. Cal., 06/15/2026
• Venue Allegations: Venue is asserted based on Defendants maintaining a regular and established place of business in Fountain Valley, California, which is within the Central District of California.
• Core Dispute: Plaintiff alleges that Defendants' solid-state drive (SSD) products infringe three patents related to high-performance memory controller architecture and storage device management.
• Technical Context: The technology concerns methods for improving the speed, security, and longevity of solid-state storage devices by optimizing data transfers, managing different types of memory, and reducing wear on flash memory cells.
• Key Procedural History: The complaint alleges that the asserted patents have been widely cited as prior art in patent applications by major technology companies, including Intel, Samsung, Micron, and Microsoft. The complaint also notes that Plaintiff's predecessor, BiTMICRO Networks, engaged in patent marking for products it contended were covered by the asserted patents, including by affixing patent numbers to product labels and providing notice via a URL.

Case Timeline

Date	Event
2006-03-17	'389 Patent Application Filed
2009-09-04	'190 Patent Priority Date
2009-09-14	'103 Patent Priority Date
2010-05-11	'389 Patent Issued
2010-09-04	'190 Patent Application Filed
2015-07-20	'103 Patent Application Filed
2015-09-15	'190 Patent Issued
2016-11-01	'103 Patent Issued
2026-06-15	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,716,389 - "Direct Memory Access Controller with Encryption and Decryption for Non-blocking High Bandwidth I/O Transactions"

• Patent Identification: U.S. Patent No. 7,716,389, titled "Direct Memory Access Controller with Encryption and Decryption for Non-blocking High Bandwidth I/O Transactions," issued May 11, 2010.

The Invention Explained

• Problem Addressed: The patent's background describes that performing security functions like encryption or decryption on data during high-speed transfers can create a bottleneck Compl. ¶16 '389 Patent, col. 2:4-26 Traditional methods require extra "memory-to-memory" transfers, where data is moved from an I/O device to memory, then read back from memory to a processing module, and finally written back to memory, which reduces speed and efficiency '389 Patent, col. 1:49-62
• The Patented Solution: The invention proposes attaching a dedicated "Data Processing Core" (DPC) to the system that can intercept Direct Memory Access (DMA) transfers on-the-fly '389 Patent, abstract An address comparator within the DPC monitors DMA requests and, if a request targets a specific address range, it signals a "DPC Hit," causing the data to be routed through the DPC for encryption or decryption before it reaches its final destination, thereby eliminating the extra memory-to-memory transfer steps '389 Patent, col. 5:21-42 '389 Patent, Fig. 3
• Technical Importance: This architecture allows a storage controller to perform high-speed, secure data transfers for multiple I/O devices simultaneously without degrading system performance, a critical function for enterprise and data center storage '389 Patent, abstract

Key Claims at a Glance

• The complaint asserts independent claim 19 Compl. ¶33
• The essential elements of claim 19, a means-plus-function claim, are:
  • A means for performing a DMA data transfer, including at least one DMA engine.
  • A means for performing data processing (encryption or decryption) coupled to the DMA transfer means, which responds to a "DPC hit signal" by using a "DPC channel to intercept said data."
• The complaint reserves the right to assert other claims Compl. ¶39

U.S. Patent No. 9,135,190 - "Multi-Profile Memory Controller for Computing Devices"

• Patent Identification: U.S. Patent No. 9,135,190, titled "Multi-Profile Memory Controller for Computing Devices," issued September 15, 2015.

The Invention Explained

• Problem Addressed: The patent identifies a drawback of conventional memory controllers that are designed to work with a single type of memory, which is suboptimal because different data access patterns (e.g., sequential vs. random) have different performance characteristics on different memory types '190 Patent, col. 1:21-44
• The Patented Solution: The invention describes a "multi-profile" memory controller that manages a memory store containing locations with different characteristics '190 Patent, abstract The controller uses "device profiles," which contain attributes of the memory locations (e.g., block size, page size, protocol type), to perform memory transactions '190 Patent, col. 3:14-25 '190 Patent, col. 3:40-54 It can select a memory location with a profile that is "optimal" for the data type being transferred (e.g., directing sequential data to a location with a large block size) '190 Patent, col. 9:5-24
• Technical Importance: This technology enables the creation of hybrid storage systems that can intelligently route data to the most appropriate type of memory, thereby optimizing overall performance for mixed workloads '190 Patent, col. 2:44-53

Key Claims at a Glance

• The complaint asserts independent claim 59 Compl. ¶47
• The essential elements of claim 59 are:
  • A memory controller with an interface controller, a memory device interface, an I/O device interface, and a memory store.
  • The interface controller performs a memory transaction by addressing a first memory location, where the first and a second memory location are associated with first and second different "device profiles."
  • The first device profile is "optimal" for the data type (random or sequential).
  • The controller identifies command details, obtains attributes from the first device profile, and uses those attributes to perform the addressing, including selecting a transfer size.
• The complaint reserves the right to assert other claims Compl. ¶53

U.S. Patent No. 9,484,103 - "Electronic Storage Device"

• Patent Identification: U.S. Patent No. 9,484,103, titled "Electronic Storage Device," issued November 1, 2016.

The Invention Explained

• Technology Synopsis: The patent addresses the problem of limited write endurance in flash memory devices by disclosing a method to reduce erase cycles '103 Patent, col. 1:33-46 The solution involves organizing a logical storage unit (a "flop") into multiple "flop sections" and using a "selection sequence" to determine the next available location for a write operation, thereby distributing writes and minimizing the need for block erasures '103 Patent, abstract '103 Patent, claim 10

Key Claims at a Glance

• Asserted Claims: The complaint asserts at least independent claim 10 Compl. ¶61
• Accused Features: The complaint alleges that the Kingston KC3000 SSDs, which use a "Phison E18 controller" and "3D TLC NAND" memory, infringe this patent Compl. ¶62 Compl. ¶63

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are the Kingston DC3000ME PCIe NVMe U.2 SSD and the Kingston KC3000 PCIe 4.0 NVMe M.2 SSD, along with their related product series Compl. ¶34 Compl. ¶48 Compl. ¶62

Functionality and Market Context

The accused products are high-performance solid-state drives marketed for data center and consumer applications Compl. ¶35 Compl. ¶49 The complaint alleges the DC3000ME implements "AES 256-bit encryption," which is asserted to be an infringing feature under the '389 patent Compl. ¶35 For the KC3000, the complaint identifies its use of "3D TLC NAND" memory and a "Phison E18 controller" as bearing on infringement of the '190 and '103 patents Compl. ¶49 Compl. ¶63 The complaint includes a photograph of a 'BiTMICRO Ace Drive II' product, which displays patent numbers, including the '190 patent, on its label Compl. p. 6

IV. Analysis of Infringement Allegations

The complaint references, but does not include, claim chart exhibits. The following tables summarize the infringement allegations based on the narrative provided in the complaint.

'389 Patent Infringement Allegations

Claim Element (from Independent Claim 19)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
A direct memory access controller for transferring data to or from a memory, and for encrypting or decrypting said data upon receiving a data processing request, the direct memory access controller comprising:	The complaint alleges the Kingston DC3000ME SSD is or contains an infringing direct memory access controller.	¶34	col. 10:50-54
a means for performing a DMA data transfer, said means for performing a DMA data transfer including at least one DMA engine configured for transferring data;	The DC3000ME, as an NVMe SSD, necessarily performs DMA data transfers to move data between the host system and its internal memory.	¶34; ¶35	col. 10:55-57
a means for performing data processing coupled to said means for performing a DMA data transfer, said data processing includes encrypting or decrypting said data in response to a DPC hit signal by at least using a DPC channel to intercept said data, causing said data to be transferred to said means for performing data processing.	The DC3000ME advertises "AES 256-bit encryption for ultimate data security," which the complaint alleges is the data processing performed by intercepting data during the DMA transfer.	¶35	col. 10:58-63

'190 Patent Infringement Allegations

Claim Element (from Independent Claim 59)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
A memory controller comprising: an interface controller coupled to a memory device interface and an input/output (IO) device interface; a memory store;	The complaint alleges the Kingston KC3000 SSD contains an infringing memory controller, identified as the Phison E18, and a memory store, identified as the 3D TLC NAND.	¶48; ¶49	col. 18:34-37
said interface controller disposed to perform a memory transaction by addressing a first memory location...said first memory location and a second memory location respectively associated with a first device profile and a second device profile;	The Phison E18 controller allegedly manages the 3D TLC NAND by addressing memory locations that have different characteristics, which the complaint maps to the claimed "device profiles."	¶49	col. 18:38-43
wherein said first device profile is optimal for a data type subject to the memory transaction, wherein said data type comprises one of a random data type or a sequential data type;	The complaint alleges the Phison E18 controller selects memory locations with profiles that are optimal for the type of data being written (e.g., random or sequential).	¶49	col. 18:44-48
said interface controller identifies command details for causing the memory transaction to be performed...said device profile representing a first set of attributes of said first memory location...and a difference exists between said first and second device profiles;	The controller allegedly uses attributes from different profiles to manage memory, where these profiles differ from one another.	¶49	col. 18:49-58
said interface controller obtaining the first set of attributes after identifying the command details; and said addressing of said first memory location includes using said attributes from said first device profile;	The Phison E18 controller allegedly obtains and uses the attributes from the selected device profile to execute the memory transaction.	¶49	col. 18:59-62

• Identified Points of Contention:
  • Scope Questions ('389 Patent): Claim 19 is a means-plus-function claim. Infringement requires showing the accused device performs the claimed function using a structure that is identical or equivalent to the "Data Processing Core" (DPC) architecture disclosed in the patent specification '389 Patent, Fig. 3 '389 Patent, col. 5:36-61 A central question will be whether Kingston's SSD controller is structurally equivalent to the patent's DPC, which includes a distinct address comparator and DPC engines for intercepting data based on a "DPC Hit" signal.
  • Technical and Definitional Questions ('190 Patent): The dispute may focus on whether the accused Phison E18 controller actually uses a system of "device profiles" as claimed. Kingston may argue that its controller manages memory using a different, non-infringing algorithm. The construction of "device profile" and "optimal" will be critical. The court will have to determine if the controller's functionality for managing different NAND types constitutes selecting an "optimal" location based on a "profile," or if it is a more general wear-leveling or performance-balancing technique.

V. Key Claim Terms for Construction

'389 Patent, Claim 19

• The Term: "means for performing data processing...to intercept said data"
• Context and Importance: This term is the functional heart of claim 19. As a means-plus-function limitation, its scope is tied to the corresponding structure described in the patent. Practitioners may focus on this term because its construction will determine whether any on-the-fly encryption system infringes, or only those with a specific architecture.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: A party might argue the function is simply intercepting and processing data during a DMA transfer, and any structure that achieves this is equivalent.
  • Evidence for a Narrower Interpretation: A party will likely point to the detailed description and Figure 3, arguing the structure is strictly the disclosed "Data Processing Core" (206, 324) comprising an "Address Comparator" (314) that generates a "DPC Hit" signal (315) to route data to dedicated "DPC Engines" (321) for processing, distinguishing it from other architectures '389 Patent, col. 5:36-54

'190 Patent, Claim 59

• The Term: "device profile"
• Context and Importance: The existence and use of a "device profile" by the accused controller is a prerequisite for infringement. The definition of this term will be a central point of dispute.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification defines an attribute as a "characteristic of a memory location" and states a device profile "may be used to represent at least one attribute" '190 Patent, col. 3:1-6 '190 Patent, col. 3:17-19 This could support an argument that any set of stored characteristics about a memory region constitutes a "device profile."
  • Evidence for a Narrower Interpretation: The patent provides specific examples of device profiles as structured tables with enumerated attributes like "Page Size," "Block Size," and "Memory Protocol" '190 Patent, Figs. 2A-2C A party may argue the term is limited to such explicit, formally defined data structures used by the controller, not just inherent characteristics of the memory.

VI. Other Allegations

• Indirect Infringement: The complaint alleges inducement of infringement for all three patents, stating that Kingston provides products and "instructions on their use to customers and others" who then operate the devices in an infringing manner Compl. ¶40 Compl. ¶54 Compl. ¶68 The basis for this allegation is Kingston's marketing and sale of the products through its website, which includes product specifications Compl. ¶40 Compl. ¶54 Compl. ¶68
• Willful Infringement: The complaint alleges Kingston has known of the asserted patents "since at least the date of service of this Complaint" Compl. ¶38 Compl. ¶52 Compl. ¶66 This allegation provides a basis for potential enhanced damages for any infringement occurring after the lawsuit was filed but does not allege pre-suit knowledge.

VII. Analyst's Conclusion: Key Questions for the Case

1. A core issue for the '389 patent will be one of structural equivalence: does the controller architecture in Kingston's DC3000ME SSD, which performs encryption, contain the specific structural elements (or their equivalents) of the "Data Processing Core"-including a dedicated address comparator and processing engines activated by a "hit" signal-as disclosed in the patent and required to satisfy the means-plus-function claim limitations?

2. A central question for the '190 and '103 patents will be one of operational mapping: does the accused Phison E18 controller's method for managing 3D TLC NAND memory constitute the use of "device profiles" to select "optimal" memory locations as claimed in the '190 patent, and does it implement the specific "flop section" and "selection sequence" logic for minimizing erase cycles as claimed in the '103 patent, or do these off-the-shelf components operate using distinct, non-infringing techniques?

3. An evidentiary question will relate to damages and notice: can BiTMICRO establish that its predecessor's patent marking practices, including product labels and a website URL, provided constructive notice to Kingston prior to the lawsuit, which would be necessary to recover pre-suit damages under 35 U.S.C. § 287?